Prosecution Insights
Last updated: April 19, 2026
Application No. 18/366,938

THIN FILM TRANSISTOR AND METHOD OF MANUFACTRUTING THIN FILM TRANSISTOR

Non-Final OA §103
Filed
Aug 08, 2023
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toppan Inc.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
2y 8m
To Grant
87%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allow Rate
488 granted / 793 resolved
-6.5% vs TC avg
Strong +25% interview lift
Without
With
+25.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
52 currently pending
Career history
845
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
48.9%
+8.9% vs TC avg
§102
16.9%
-23.1% vs TC avg
§112
27.2%
-12.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 793 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Group I, Species A represented by figure 1 and claims 1-17 in the reply filed on March 9, 2026 is acknowledged. The traversal is on the ground(s) that Examiner has not provided sufficient reasons to support a conclusion that species are independent or distinct. This is not found persuasive because under MPEP 806.04(f) an election of species is proper if the species are mutually exclusive of each other. Examiner on page 4 of the Election/Restriction dated January 9, 2026, explained how each of the species are mutually exclusive of each other. The basis of the election of species is the presence of the gate insulating film and its location if present Therefore, this argument is unpersuasive. Applicant next argues there would be no serious burden upon Examiner. However, this is a conclusory statement with no evidentiary support. Applicant does not explain why there is no burden, nor does Applicant point to any reference evidencing there is no burden. Therefore, this argument is not persuasive. The requirement is still deemed proper and is therefore made FINAL. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on August 8, 2023; July 23, 2024; November 27, 2024; and January 17, 2024 were considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 7, 11, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2015/0129864 A1) (“Hsu”), in view of Miki et al. (US 2015/0228674 A1) (“Miki”). Regarding claims 1-2, Hsu teaches at least in figure 1: a flexible substrate (110) having a support surface (top surface of 110); a gate electrode layer (120) formed at a first part of the support surface (where 120 is formed; hereinafter “A”); a gate insulating layer (130) covering a second part of the support surface (where 120 is not on the surface of 120; hereinafter “B”) and the gate electrode layer (120); a semiconductor layer (140) formed such that the semiconductor layer (140) and the gate electrode layer (120) is sandwiching the gate insulating layer (130); a source electrode layer (160) formed in contact with a first end of the semiconductor layer (140); and a drain electrode layer (170) formed in contact with a second end of the semiconductor layer (140), wherein the gate insulating layer (130) includes a first gate insulating film (130) comprising an organic polymer compound (¶ 0029, where 130 can be an organic polymer compound) and covering the second part (B) and the gate electrode layer (130), and a second gate insulating film (150) comprising an inorganic silicon compound (¶ 0032) and sandwiched between the first gate insulating film (130) and the semiconductor layer (140), the second gate insulating film (150) has a thickness in a range of 2 nm to 30 nm (¶ 0034, where 150 can be 100-1000 Angstroms (10-100nm). Hsu does not teach: the second gate insulating film has a hydrogen content in a range of 2 at % to 15 at %. Miki teaches: The gate insulating film touching an active layer has a hydrogen content in a range of 2 at % to 15 at %. (¶¶ 0034-37). It would have been obvious to one of ordinary skill in the art to control the hydrogen concentration of the gate insulating film touching the active layer to be 4 at % or less. This is because the resistance to bias stress and light+ negative bias stress is significantly improved. Id. Based upon the teachings of Miki, it would have been obvious to one of ordinary skill in the art to reduce the hydrogen content in the second gate insulating film (150) of Hsu as this is the gate insulating film which is touching the semiconductor layer of Hsu. Regarding claims 7, 11, and 15, Hsu teaches at least in figure 1: wherein the semiconductor layer (140) is an oxide semiconductor layer comprising indium (¶ 0030). Regarding claim 3, Claim 1 teaches all of the limitations of claim 2 with the exception of: The gate insulating film touching an active layer has a hydrogen content in a range of 6 at % to 15 at %. The prior art teaches 4%. However, under Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783 (Fed. Cir. 1985) a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. MPEP 2144.05. Here, there is 1 at% difference between the claim and the prior art. Therefore, “[t]he proportions are so close that prima facie one skilled in the art would have expected them to have the same properties.” As a result, claim 3 is obvious. Regarding claim 4, Claim 4 is based upon claim 2 in is obvious for the reasons stated in claim 3. Where claim 4 has a 2 at% difference. The analysis of the claim 4 does not change the result presented in claim 3, and is rejected for those reasons. Claim(s) 5-6, 8-10, 12-14, and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, in view of Miki, in view of Kotake et al. (US 9,166,182 B2) (“Kotake”) Regarding claims 5, 9, 13, and 17, Hsu teaches at least in figure 1: the prior art in ¶ 0029 teaches the same or similar material, as Applicant does in the specification at pg. 12 at lines 15-22. Regarding the second gate insulating film relative permittivity εB, The prior art in ¶ 0032 teaches the same material, or similar material, as Applicant does in the specification at pg. 13 at lines 16-20. Regarding the second gate insulating film thickness dB, As stated in claim 1 the prior art teaches the same or similar range of the gate insulating film thickness. Hsu Does not teach: What the first gate insulating film thickness dA is. Therefore, it would have been obvious to one of ordinary skill in the art to search for a reference which teaches this missing thickness. Kotake teaches: That organic gate insulating films, like the one taught by Hsu, can have a thickness of about 1 micrometer. Col. 11 at lines 24-40. The combination of Hsu and Kotake teach: the gate insulating layer satisfies formula (1), 0.001≤(εA/dA)/(εB/dB)<0.015. The combination teaches this because the prior art in combination teaches the same, or similar, materials and thicknesses as Applicant. Therefore, the inequality above is a matter of optimizing the materials and thicknesses of said materials. This is because the general conditions are disclosed in the prior art, and it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). Thus optimization of the claim would be obvious to one of ordinary skill in the art. Regarding claims 6, 8, 10, 12, 14 and 16, the prior art teaches: wherein a relative permittivity of the first gate insulating film is lower than a relative permittivity of the second gate insulating film (See claim 5 above where Hsu teaches the same or similar materials), and the first gate insulating film has a thickness in a range of 300 nm to 2500 nm (see claim 5 above where Kotake teaches a thickness in the middle of the claimed range). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Aug 08, 2023
Application Filed
Mar 19, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604480
Ferroelectric Memory Device and Method of Forming the Same
2y 5m to grant Granted Apr 14, 2026
Patent 12588499
INTEGRATED CIRCUIT HEAT SPREADER INCLUDING SEALANT INTERFACE MATERIAL
2y 5m to grant Granted Mar 24, 2026
Patent 12581688
SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
2y 5m to grant Granted Mar 17, 2026
Patent 12581808
ELECTROLUMINESCENT DISPLAY DEVICE
2y 5m to grant Granted Mar 17, 2026
Patent 12581747
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
87%
With Interview (+25.4%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 793 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month