DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 and 15-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE et al. (US 20130256828 A1, hereinafter Lee)
With regards to claim 1, Lee discloses an integrated circuit (IC) device (FIGS. 15A-15C) comprising:
a substrate (substrate 101) having a plurality of active regions; (active regions 12)
a plurality of word lines (word lines 115) extending in a first horizontal direction (Y direction) across the plurality of active regions; (see FIG. 15C)
a plurality of bit lines (bit lines 141) extending on the substrate in a second horizontal direction (X direction) perpendicular to the first horizontal direction;
a plurality of conductive vertical structures comprising a plurality of conductive expanded pads (node contact 157) and a plurality of conductive contact plugs, (landing pad 159) wherein the plurality of conductive expanded pads are closer to a bottom surface of the substrate than the plurality of bit lines and are in contact with the plurality of active regions, (See FIG. 15B) and the plurality of conductive contact plugs extend in a vertical direction and are connected to the plurality of conductive expanded pads between each of the plurality of bit lines; (See FIG. 15B) and
a plurality of separation fences (insulation layers 121, 129, 143, 147 and 149) separating the plurality of conductive vertical structures from each other in the second horizontal direction, (See FIG. 15C and response to Arguments) between each of the plurality of bit lines, and having sidewalls extending linearly in contact with the plurality of conductive vertical structures. (See FIG. 15B)
With regards to claim 2, Lee discloses the IC device of claim 1, wherein lower surfaces of the plurality of separation fences are closer to the bottom surface of the substrate than lower surfaces of the plurality of conductive expanded pads. (See FIG. 15B)
With regards to claim 3, Lee discloses the IC device of claim 1, wherein a sidewall of a first separation fence among the plurality of separation fences comprises:
a first portion (layer 121) facing one of the plurality of conductive expanded pads; and
a second portion (layer 147) facing one of the plurality of conductive contact plugs, and wherein the first portion and the second portion are integrated with each other. (See FIG. 15B, showing the integration)
With regards to claim 4, Lee discloses the IC device of claim 1, wherein a central axis of each of the plurality of separation fences is perpendicular to the substrate. (See FIG. 15B)
With regards to claim 5, Lee discloses the IC device of claim 1, wherein lower surfaces of the plurality of conductive expanded pads are coplanar with an upper surface of the substrate. (See FIG. 15B, showing the coplanarity)
With regards to claim 6, Lee discloses the IC device of claim 1, wherein each of the plurality of conductive expanded pads extends through an upper surface of the substrate. (See FIG. 15B)
With regards to claim 7, Lee discloses the IC device of claim 1, wherein the plurality of separation fences at least partially overlap the plurality of word lines in the vertical direction. (see FIG. 15C)
With regards to claim 8, Lee discloses the IC device of claim 1, wherein the plurality of conductive expanded pads comprise any one or any combination of a metal, a doped polysilicon layer, and an epitaxially grown silicon layer. (Paragraph [0057]: “storage node contacts 157 may be formed by depositing and planarizing a polysilicon layer, a metal silicide layer, a metal nitride layer, a metal layer, and so forth. In other example embodiments, the storage node contacts 157 may be an epitaxially grown silicon layer.”)
With regards to claim 9, Lee discloses the IC device of claim 1, further comprising:
a plurality of direct contacts (direct contact 135) connected between the plurality of bit lines and the plurality of active regions; and
a plurality of pad isolation structures (spacer 133) spaced apart from each other in the second horizontal direction with the plurality of direct contacts therebetween, and separating the plurality of conductive expanded pads in the first horizontal direction. (see FIG. 15B)
With regards to claim 10, Lee discloses the IC device of claim 9, further comprising an interlayer insulating layer (layer 143 above spacer 133) between the plurality of pad isolation structures and the plurality of bit lines. (see Fig. 15B)
With regards to claim 11, Lee discloses an integrated circuit (IC) device (FIGS. 15A-15C) comprising:
a substrate (substrate 101) having a plurality of active regions; (active regions 12)
a plurality of word lines (word lines 115) extending in a first horizontal direction across the plurality of active regions; (FIG. 15B)
a plurality of conductive expanded pads (node contacts 157) on the substrate and connected to the plurality of active regions;
a plurality of pad isolation structures (spacers 133) located between the plurality of conductive expanded pads;
a plurality of direct contacts (direct contact 135) connected to the plurality of active regions;
a plurality of bit lines (bit lines 141) extending in a second horizontal direction perpendicular to the first horizontal direction, on the plurality of direct contacts and the plurality of pad isolation structures, and connected to the plurality of direct contacts; (see FIG. 15B)
a plurality of conductive plugs (landing pad 159) extending in a vertical direction on the plurality of conductive expanded pads and connected to the plurality of conductive expanded pads; and
a plurality of separation fences (insulation layers 121, 129, 143, 147 and 149) passing through the plurality of conductive expanded pads and the plurality of conductive plugs, separating the plurality of conductive expanded pads from each other in the second horizontal direction, (See FIG. 15C showing the separation and response to Arguments) and having sidewalls extending linearly in the vertical direction. (See FIG. 15B)
With regards to claim 12, Lee discloses the IC device of claim 11, wherein a central axis of each of the plurality of separation fences is perpendicular to the substrate. (see FIG. 15B)
With regards to claim 13, Lee discloses the IC device of claim 11, wherein lower surfaces of the plurality of conductive expanded pads are coplanar with an upper surface of the substrate. (See FIG. 15B)
With regards to claim 15, Lee discloses the IC device of claim 11, wherein the plurality of separation fences at least partially overlap the plurality of word lines in the vertical direction. (See FIG. 15C)
With regards to claim 16, Lee discloses the IC device of claim 11, further comprising an interlayer insulating layer (layer 143 above spacer 133) between the plurality of pad isolation structures and the plurality of bit lines. (see Fig. 15B)
With regards to claim 17, Lee discloses an integrated circuit (IC) device (FIGS. 15A-15C) comprising:
a substrate (substrate 101) having a plurality of active regions (active regions 12) spaced apart from each other;
a plurality of word lines (word lines 115) extending in a first horizontal direction across the plurality of active regions; (FIG. 15B)
a plurality of bit line structures (bit lines 141) spaced apart from each other in the first horizontal direction on the substrate and comprising a plurality of bit lines (bit lines 141) and a plurality of spacer structures, (layer 143) wherein the plurality of bit lines extend in a second horizontal direction intersecting the first horizontal direction, and the plurality of spacer structures are provided on both sidewalls of the plurality of bit lines; (See FIG. 15B)
a plurality of direct contacts (direct contact 135) connecting the plurality of active regions to the plurality of bit lines; (See FIG. 15B)
a plurality of pad isolation structures (spacers 133) spaced apart from each other in the second horizontal direction with the plurality of direct contacts therebetween, wherein the plurality of pad isolation structures are between
a plurality of conductive vertical structures comprising a plurality of conductive expanded pads (node contacts 157) and a plurality of conductive contact plugs, (landing pad 159) wherein the plurality of conductive expanded pads are spaced apart from each other in the first horizontal direction with the plurality of pad isolation structures therebetween, and the plurality of conductive contact plugs are in contact with the plurality of conductive expanded pads and extend in a vertical direction; (See FIG. 15B) and
a plurality of separation fences (separation fences 147/121/129/149) arranged between the plurality of conductive vertical structures in the second horizontal direction, (See FIG. 15C and Response to Arguments) between the plurality of conductive vertical structures, and having side surfaces extending linearly adjacent an interface between the plurality of conductive expanded pads and the plurality of conductive contact plugs. (See FIG. 15B)
With regards to claim 18, Lee discloses the IC device of claim 17, wherein lower surfaces of the plurality of separation fences are closer to the lower surface of the substrate than lower surfaces of the plurality of conductive expanded pads. (see FIG. 15B, showing the fence 121 closer to the bottom of substrate 101)
With regards to claim 19, Lee discloses the IC device of claim 17, wherein each of the plurality of separation fences comprises:
a first portion (layer 121) facing one of the plurality of conductive expanded pads; and
a second portion (layer 147) facing one of the plurality of conductive contact plugs, and wherein the first portion and the second portion are integrated with each other. (see FIG. 15B, showing the integration via layer 143)
With regards to claim 20, Lee discloses the IC device of claim 17, wherein a central axis of each of the plurality of separation fences is perpendicular to the substrate. (See Fig. 15B)
Response to Arguments
Applicant's arguments filed 05/06/2026 have been fully considered but they are not persuasive.
Examiner notes that the separation fences now include layer 149, which is shown to be between the conductive vertical structures 157/159, thus teaching the features of at least claims 1, 11, and 17. Therefore, claims 1, 11, and 17 are properly rejected, and claims 2-10, 12-13, 15-16, and 18-20 are rejected for at least their dependencies.
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al. (US 20190088739 A1) – Different spacers/fences in a memory device.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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