DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 2 in the reply filed on 2/3/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7-8, 10 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lee et al (US 2022/0092249).
1. An integrated circuit including a standard cell (Figs.3-5 (SC) and [0046]) having a cell height in a first horizontal direction, wherein the standard cell (Figs.3-5 (SC) and [0046]) comprises:
a metal layer (Fig.3-5 (M1(PL1/PL2)) and [0034-0035]) including a pattern extending in the first horizontal direction and a plurality of tracks spaced apart from one another in a second horizontal direction [0034]; and
at least one via (Fig.8C-8F (V0/V1) and [0095]) connecting the metal layer (Fig.3-5 (M1(PL1/PL2)) and [0034-0035]) to a lower pattern of the metal layer (Fig.8C-8F (CM/M1(S)) and [0095]), wherein the plurality of tracks comprise a plurality of cell tracks (Fig.3 (M1(PL1/PL2)) and [0034-0035]) and at least one power distribution network (PDN) track (Figs. 3-5 (M2(PDN1)/M2 (PDN2)) and [0047]), wherein cell patterns are formed on the plurality of cell tracks (Fig.3-5 (M1(PL1/PL2)) and [0034-0035]), and a PDN pattern (Figs. 3-5 (M2(PDN1)/M2 (PDN2)) and [0047]) or a routing pattern [0054] is formed on the at least one power distribution network (PDN) track (Figs. 3-5 (M2(PDN1)/M2 (PDN2)) and [0047]), wherein a first pattern (Figs.3-5 (M2(N)) and [0047-0048]) is spaced apart from a cell boundary (Figs.3-5 (B1/B2) and [0046]) of the standard cell (Figs.3-5 (SC) and [0046]) by a first length [0061] and is formed on a first cell track among the plurality of cell tracks, and wherein a second pattern (Figs. 3-5 (M2(P)) and [0056]) is spaced apart from a cell boundary (Figs.3-5 (B1/B2) and [0046]) of the standard cell (Figs.3-5 (SC) and [0046]) by a second length [0060] that is different from the first length [0061] and is formed on a second cell track among the plurality of cell tracks (Fig.3-5 (M1(PL1/PL2)) and [0034-0035]).
7. The integrated circuit of claim 1, wherein the standard cell is continuously placed in a first row with a first height and a second row with a second height (Figs.3-5 (SC) and [0046]).
8. The integrated circuit of claim 7, wherein the first height is equal to the second height (Figs.3-5 (SC) and [0046]).
10. An integrated circuit including a standard cell (Figs.3-5 (SC) and [0046]) defined by a cell boundary (Figs.3-5 (B1/B2) and [0046]), wherein the standard cell (Figs.3-5 (SC) and [0046]) comprises: a first metal layer (Fig.8C-8F (CM/M1(S)) and [0095]) and a second metal layer (Fig.3-5 (M1(PL1/PL2)) and [0034-0035]) that are sequentially stacked on a substrate, and in each of the first metal layer (Fig.8C-8F (CM/M1(S)) and [0095]) and the second metal layer (Fig.3-5 (M1(PL1/PL2)) and [0034-0035]), a plurality of patterns are formed; and at least one via (Fig.8C-8F (V0/V1) and [0095]) electrically connecting a pattern of the first metal layer (Fig.8C-8F (CM/M1(S)) and [0095]) to a pattern of the second metal layer(Fig.3-5 (M1(PL1/PL2)) and [0034-0035]), wherein, on the second metal layer (Fig.3-5 (M1(PL1/PL2)) and [0034-0035]), a pattern (Figs.3-5 (M2(N)/ M2 (P)) and [0047-0048/0056]) extending in a first horizontal direction is formed and a plurality of tracks spaced apart from one another in a second horizontal direction are defined, wherein the plurality of tracks comprise a plurality of cell tracks (Figs.3-5 (M2(N)/ M2 (P)) and [0047-0048/0056]) and at least one power distribution network (PDN) track (Figs. 3-5 (M2(PDN1)/M2 (PDN2)) and [0047]), wherein cell patterns are formed on the plurality of cell tracks (Figs.3-5 (M2(N)/ M2 (P)) and [0047-0048/0056]), and a PDN pattern (Figs. 3-5 (M2(PDN1)/M2 (PDN2)) and [0047]) or a routing pattern [0054] is formed on the at least one power distribution network (PDN) track (Figs. 3-5 (M2(PDN1)/M2 (PDN2)) and [0047]), wherein a first pattern (Figs.3-5 (M2(N)) and [0047-0048]) is spaced apart from a cell boundary (Figs.3-5 (B1/B2) and [0046]) of the standard cell (Figs.3-5 (SC) and [0046]) by a first length [0061] and is formed on a first cell track (Figs.3-5 (M2(N)) and [0047-0048]) among the plurality of cell tracks(Figs.3-5 (M2(N)/ M2 (P)) and [0047-0048/0056]), and wherein a second pattern (Figs. 3-5 (M2(P)) and [0056]) is spaced apart from a cell boundary (Figs.3-5 (B1/B2) and [0046]) of the standard cell (Figs.3-5 (SC) and [0046]) by a second length [0060] that is different from the first length [0061] and is formed on a second cell track (Figs. 3-5 (M2(P)) and [0056]) among the plurality of cell tracks (Figs.3-5 (M2(N)/ M2 (P)) and [0047-0048/0056]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is/are rejected under 35 U.S.C. 103 as being obvious over Lee et al (US 2022/0092249).
Lee teaches the limitations of claims 1 and 7 as cited above, however fails to explicitly teach the limitation of claim 9 as follows:
9. The integrated circuit of claim 7, wherein the first height is different from the second height.
Although Lee’s drawings show both cells having the same height, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee’s teachings to include a first and second sell having different heights because height variation is a matter of design choice and is a well-known and easily manipulated design variable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Do et al (US 20220122970); Jung et al (US 2022/0344463); and Morrow et al (US 11139241) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
4/3/26
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