Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119
(a)-(d) to foreign application KR 10-2022-0115802 filed on 10/03/2023. The foreign application is not in English. The certified copy of the foreign priority application has been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
To be entitled to the filing date of the foreign priority application JP 2021108104 that is not in English, an English translation of the non-English language KR 10-2022-0115802 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Response to Arguments
Applicant’s arguments, see page 4, line 7-page 8 line 22, filed 6/23/2026, with respect to the rejection(s) of claims 1, 9 and 19 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yang et al. (US Pub 20220037253), hereinafter referred to as Yang, Choi et al, IEEE Transactions on Electron Devices , Vol. 66, No 11 (November 2019), hereinafter referred to as Choi, Cho et al. (US Pub. 20210217473), hereinafter referred to as Cho and Baturay, Ş. Conversion from p- to n-Type Conductivity in CuO Thin Films Through Zr Doping. J. Electron. Mater. 51, 5644–5654 (2022). https://doi.org/10.1007/s11664-022-09836-9, hereinafter referred to as Baturay, in the cases of claims 1 and 19, and Yang, Cho, Choi, Baturay Selim (US Pub. 20210119068), hereinafter referred to as Selim, and Wu et al. (US Pub. 20220195201), hereinafter referred to as Wu in the case of claim 9.
Applicant’s arguments, see page 9, line 1- page 11 line 17, filed 6/23/2026, with respect to the rejection of claim 8 under 35 U.S.C. § 103, and new claim 21 have been fully considered and are persuasive. Therefore, the rejection to claim 8 has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Yang, Selim, and Wu in respect to claim 8, and under Yang, Cho Selim and Wu in the case of claim 21.
Applicant’s arguments, see page 11, line 23-page 13, line 7, filed 6/23/2026, with respect to new claim 22 have been fully considered but are moot because the new ground of rejection in view of Yang and Zhang (US Pub. 20230282280), hereinafter referred to as Zhang. does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang hereinafter referred to as Yang, Choi, Cho et al. Cho and Baturay.
Regarding claim 1, Yang teaches a semiconductor device comprising: a plurality of gate electrodes (Yang, 227, 228, 229, 247, 248, 249, 267, 268, 269, Fig. 24, paras, 29, 39) spaced apart from each other in a vertical direction on a substrate (Yang, 100, Fig. 24, para. 11); a plurality of channel structures respectively penetrating the plurality of gate electrodes and extending in the vertical direction, each of the plurality of channel structures including a channel layer having a stacked structure of a first oxide semiconductor channel layer (Tang, 424, Fig. 30, paras. 32, 42) and a second oxide semiconductor channel layer (Yang, 426, Fig. 30, para. 37), and a gate insulating layer (Yahng, 422, Fig. 30, para. 31) disposed between each gate electrode of the plurality of gate electrodes and the channel layer; and a plurality of bit lines (Yang, 720, Fig. 28, para. 48) disposed on the plurality of channel structures and respectively connected to the plurality of channel structures, wherein the gate insulating layer, the first oxide semiconductor channel layer, and the second oxide semiconductor channel layer are sequentially disposed with the first oxide semiconductor channel layer between the second oxide semiconductor channel layer and the gate insulating layer (Yang, Fig. 24).
Yang does teach that the first oxide layer may be an IGZO layer (Yang, para. 32) and that the second oxide layer may be a high-k dielectric material, but Yang is mute on the conductivity types of these materials.
However, Choi teaches that IGZO may be n-type conductivity (Choi, Section II, para. 3).
Additionally, Cho teaches a memory cell wherein the first oxide layer (Cho, 522, Fig. 6A, para. 95) may be IGZO and the second oxide layer (Cho, 523, Fig. 6A, para. 97) is made of an oxide, which may include copper oxide. According to Baturay, CuO exhibits monoclinic p-type conductivity for depositing a variety of devices (Baturay, Introduction, para. 1).
Therefore it would be obvious to one having ordinary skill in the art to replace the second oxide of Yang with the copper oxide of Cho in order to allow resistance change depending on applied voltage (Cho, para. 97).
Regarding claim 2, modified Yang teaches the semiconductor device as claimed in claim 1, wherein: the first oxide semiconductor channel layer has an n-type conductivity (Choi, section II, para. 3, states IGZO may be n-type conductivity) and has a first thickness on the gate insulating layer (Yang, Fig. 24),
and the second oxide semiconductor channel layer has a p-type conductivity (Baturay, Introduction, para. 1) and has a second thickness on the gate insulating layer(Yang, Fig. 24).
Regarding claim 19, Yang teaches an electronic system comprising: a main substrate (Yang, 100, Fig. 24, para. 11);
a semiconductor device on the main substrate (Yang, Fig. 24);
and a controller electrically connected to the semiconductor device on the main substrate (Yang, para. 13),
wherein the semiconductor device includes:
a plurality of gate electrodes (Yang, 227, 228, 229, 247, 248, 249, 267, 268, 269, Fig. 24, paras, 29, 39) spaced apart from each other in a vertical direction on the main substrate (Yang, 100, Fig. 24, para. 11);
a plurality of channel structures (Yang, 424, 426, 422, Fig. 30B, paras. 31, 32, 37, 42) respectively penetrating the plurality of gate electrodes and extending in the vertical direction;
a plurality of bit lines (Yang 720, Fig. 28, para. 48) disposed on the plurality of channel structures and respectively connected to the plurality of channel structures;
a peripheral circuit (Yang, IN Fig. 1, para. 13) electrically connected to the plurality of gate electrodes and the plurality of bit lines;
and an input/output pad (Yang, para. 13) electrically connected to the peripheral circuit,
wherein each of the plurality of channel structures comprises a channel layer having a stacked structure of a first oxide semiconductor channel layer (Yang, 424, Fig. 30, paras. 29, 39) and a second oxide semiconductor channel layer (Yang, 426, Fig. 30, para. 37), and a gate insulating layer (Yang, 422, Fig. 24, para. 31) disposed between each gate electrode of the plurality of gate electrodes and the channel layer, and the gate insulating layer, the first oxide semiconductor channel layer, and the second oxide semiconductor channel layer are sequentially disposed with the first oxide semiconductor channel layer between the second oxide semiconductor channel layer and the gate insulating layer (Yang, Fig. 24).
Yang does teach that the first oxide layer may be an IGZO layer (Yang, para. 32) and that the second oxide layer may be a high-k dielectric material, but Yang is mute on the conductivity types of these materials.
However, Choi teaches that IGZO may be n-type conductivity (Choi, Section II, para. 3).
Additionally, Cho teaches a memory cell wherein the first oxide layer (Cho, 522, Fig. 6A, para. 95) may be IGZO and the second oxide layer (Cho, 523, Fig. 6A, para. 97) is made of an oxide, which may include copper oxide. According to Baturay, CuO exhibits monoclinic p-type conductivity for depositing a variety of devices (Baturay, Introduction, para. 1).
Therefore it would be obvious to one having ordinary skill in the art to replace the second oxide of Yang with the copper oxide of Cho in order to allow resistance change depending on applied voltage (Cho, para. 97).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yang, Choi, Cho and Baturay as applied to claim 2 above, and further in view of Tak et al. (US Pub 20210066458), hereinafter referred to as Tak.
Regarding claim 3, modified Yang teaches the semiconductor device as claimed in claim 2, but does not teach wherein the first thickness is greater than the second thickness.
However, Tak teaches a semiconductor device wherein the second channel layer (Tak, 15A, Fig.1B, para. 39) has a smaller thickness than the first channel layer (Tak, 14, Fig. 1B, para. 39)
Therefore, it would be obvious to combine the device of modified Yang with the thicknesses of Tak in order to increase carrier mobility and reduce power consumption (Tak, para. 56)
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yang, Choi, Cho and Baturay as applied to claim 1 above, and further in view Selim and Wu.
Regarding claim 8, modified Yang teaches the semiconductor device as claimed in claim 1, but does not explicitly teach wherein, a band gap of one of the first oxide semiconductor channel layer and the second oxide semiconductor channel layer having an n-type conductivity has a greater value than that of a band gap of the other having a p-type conductivity
However, Selim teaches that IGZO has a band gap of 3.42 eV (Selim, paras. 39, 72) and Wu teaches that copper oxide has a band gap of 2.0 eV (Wu, para. 69),
Therefore the requirement that the n-type layer(IGZO) has a higher bandgap value than the p-type layer (copper oxide) has been met.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yang, Choi, Cho and Baturay as applied to claim 1 above, and further in view of Zhang, hereinafter referred to as Zhang.
Regarding claim 22, modified Yang teaches the semiconductor device as claimed in claim 1, but does not teach wherein the gate insulating layer covers a lowermost portion of the channel layer.
However, Zhang teaches a semiconductor memory device wherein the gate insulating layer (Zhang, 622, Fig. 3B, para. 63) covers a lowermost portion of the channel layer.
Therefore it would have been obvious to one having ordinary skill in the art to combine the lower covering of Zhang with the structure of modified Yang on order to block the outflow of electronic charges (Zhang, para. 64).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yang, Choi, Cho and Baturay as applied to claim 19 above, and further in view of Tak, Selim and Wu.
Regarding claim 20, modified Yang teaches the electronic system as claimed in claim 19, wherein the first oxide semiconductor channel layer has an n-type conductivity (Choi, section II, para. 3) and has a first thickness on the gate insulating layer (Yang, Fig. 24),
and the second oxide semiconductor channel layer has a p-type conductivity (Baturay, Introduction, para. 1) and has a second thickness on the gate insulating layer (Yang, Fig. 24).
Modified Yang does not teach the second oxide semiconductor channel layer has a second thickness smaller than the first thickness on the gate insulating layer.
However, Tak teaches a semiconductor device wherein the second channel layer (Tak, 15A, Fig.1B, para. 39) has a smaller thickness than the first channel layer (Tak, 14, Fig. 1B, para. 39)
Therefore, it would be obvious to combine the device of modified Yang with the thicknesses of Tak in order to increase carrier mobility and reduce power consumption (Tak, para. 56).
Claims 9, 16-18 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yang, Choi, Cho, Baturay, Selim, and Wu.
Regarding claim 9, Yang teaches a semiconductor device comprising:
a gate stack including a plurality of gate electrodes (Yang, 227, 228, 229, 247, 248, 249 267, 268, 269 Fig. 24, Para. 29, 39) and a plurality of insulating layers (Yang, 217, 218, 219, 237, 238, 239, 257, 258, 259, 277, 278, 279, Fig. 24, paras. 29, 39) alternately stacked on a substrate;
a plurality of channel structures (Yang, 424, 426, 422, Fig. 30B, paras. 31, 32, 37, 42) respectively filling a plurality of channel holes penetrating the gate stack;
and a plurality of bit lines (Yang, 720, Fig. 28, para. 48) disposed on the plurality of channel structures and respectively connected to the plurality of channel structures,
wherein each of the plurality of channel structures comprises a gate insulating layer including a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer conformally and sequentially disposed on a sidewall of each of the plurality of channel holes;
and a channel layer having a stacked structure of a first oxide semiconductor channel layer (Yang, 424, Fig. 24, paras. 32, 42) and a second oxide semiconductor channel layer (Yang, 426, Fig. 24, para. 37) on the gate insulating layer,
Yang does teach that the first oxide layer may be an IGZO layer (Yang, para. 32) and that the second oxide layer may be a high-k dielectric material, but Yang is mute on the conductivity types of these materials. Yang also does not teach wherein a band gap of the first oxide semiconductor channel layer has a greater value than a band gap of the second oxide semiconductor channel layer.
However, Choi teaches that IGZO may be n-type conductivity (Choi, Section II, para. 3).
Additionally, Cho teaches a memory cell wherein the first oxide layer (Cho, 522, Fig. 6A, para. 95) may be IGZO and the second oxide layer (Cho, 523, Fig. 6A, para. 97) is made of an oxide, which may include copper oxide. According to Baturay, CuO exhibits monoclinic p-type conductivity for depositing a variety of devices (Baturay, Introduction, para. 1).
Therefore it would be obvious to one having ordinary skill in the art to replace the second oxide of Yang with the copper oxide of Cho in order to allow resistance change depending on applied voltage (Cho, para. 97).
Additionally, Selim teaches that IGZO has a band gap of 3.42 eV (Selim, paras. 39, 72) and Wu teaches that copper oxide has a band gape of 2.0eV (Wu, para. 69), therefore the use of IGZO and CuO meets the limitation that wherein a band gap of the first oxide semiconductor channel layer has a greater value than a band gap of the second oxide semiconductor channel layer.
Regarding claim 16, modified Yang teaches the semiconductor device as claimed in claim 9, wherein the first oxide semiconductor channel layer includes at least one oxide semiconductor material of a quaternary oxide semiconductor material including three different metal atoms or a quinary oxide semiconductor material including four different metal atoms (Yang, para, 32, IGZO or a quinary as described in para. 22.), and the second oxide semiconductor channel layer includes a binary oxide semiconductor material including one metal element (Cho, para. 97).
Regarding claim 17, modified Yang teaches the semiconductor device as claimed in claim 16, wherein the second oxide semiconductor channel layer includes a binary oxide semiconductor material including one same metal element among metal elements included in an oxide semiconductor material constituting the first oxide semiconductor channel layer.
Yang teaches that the first semiconductor layer may be composed of a quinary oxide semiconductor made up of Indium Gallium, Zinc, oxygen and one of titanium, aluminum, silver, silicon and tin (Yang, para. 32). Cho further describes the second semiconductor layer as being one of an oxide of at least one element selected from a group including zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), and praseodymium (Pr).
Therefore it would be obvious to one of ordinary skill in the art to conduct route experimentation on the correct materials to optimize resistance change based on the applied voltage (Cho, para. 97) while maintaining the required band gap relationship.
Regarding claim 18, modified Yang teaches the semiconductor device as claimed in claim 9, wherein the first oxide semiconductor channel layer includes at least one of indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO) (Yang, para. 32), and the second oxide semiconductor channel layer includes at least one of tin oxide (SnO), tellurium oxide (TeO), copper oxide (CuO), bismuth oxide (BiO), or nickel oxide (NiO) (Cho, para. 95)
Regarding claim 21, modified Yang teaches the semiconductor device as claimed in claim 9, wherein the band gap of the first oxide semiconductor channel layer is greater than or equal to 3 eV (Selim, para. 72, IGZO has a band gap of 3.42 eV), and the band gap of the second oxide semiconductor channel layer is less than 3 eV (Wu, para. 69, CuO has a band gap of 2.0 eV).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yang, Choi, Cho, Baturay, Selim, and Wu. as applied to claim 9 above, and further in view of Zhang. Regarding claim 10, modified Yang teaches the semiconductor device as claimed in claim 9, wherein each of the plurality of channel structures further includes: a buried insulating layer (Yang, 430, Fig. 30, para. 38) filling a space defined by the channel layer.
Yang does not teach a conductive plug contacting the channel layer and the buried insulating layer and filling an upper side of each of the plurality of channel holes.
However, Zhang does teach a semiconductor device with a conductive plug (Zhang, 68, Fig. 3B, para. 61) contacting the channel layer (Zhang, 640, Fig. 3B) and the buried insulating layer (Zhang, 660, Fig. 3B) and filling an upper side of each of the plurality of channel holes.
Therefore, it would have been obvious to one having ordinary skill in the art to combine the plug of Zhang with the structure of modified Yang on order to improve density of the memory cells (Zhang, paras. 3-4)
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yang, Choi, Cho, Baturay, Selim, and Wu. As applied to claim 9 above, and further in view of Tak.
Regarding claim 11, modified Yang teaches the semiconductor device as claimed in claim 10, wherein the first oxide semiconductor channel layer conformally covers the gate insulating layer covering the sidewall of each of the plurality of channel holes and a bottom portion of each of the plurality of channel holes to a first thickness (Yang, Fig. 24), and the second oxide semiconductor channel layer conformally covers the first oxide semiconductor channel layer to a second thickness (Yang, Fig. 24).
Modified Yang does not teach wherein the second thickness is equal to or smaller than the first thickness.
However, Tak teaches a semiconductor device wherein the second channel layer (Tak, 15A, Fig.1B, para. 39) has a smaller thickness than the first channel layer (Tak, 14, Fig. 1B, para. 39)
Therefore, it would be obvious to combine the device of modified Yang with the thicknesses of Tak in order to increase carrier mobility and reduce power consumption (Tak, para. 56).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim et al. (US Pub. 20210202833) teaches a memory device with two oxide layers and a gate insulating layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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