Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's election with traverse of Species 1A and Species IIA in the reply filed on 2 February 2026 is acknowledged. The traversal is on the grounds that Species from I(a-f) are usable with the matching species from II(a-f). This is not found persuasive because the requirement was to elect one species from each group. Examiner acknowledges that Species I(a) and Species II(a), for example, can be used together. Examiner maintains that all species I(a-f) are mutually exclusive from each other and that all species II(a-f) are mutually exclusive to one another.
The requirement is still deemed proper and is therefore made FINAL.
Claims 4-7, 12-15 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12 February 2026.
NOTE: Examiner also notes that during election response applicant selected claims 1, 2, 4, 8-11, 13 and 16-20 as corresponding to this election. However, claim 4 speaks to Species I(b) while claim 3 speaks to species I(a). Claim 3 has been examined and claim 4 withdrawn due to election of Species I(a).
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application KR 10-2022-0115802 filed on 10/03/2023. The foreign application is not in English. The certified copy of the foreign priority application has been received. Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application JP 2021108104 that is not in English, an English translation of the non-English language KR 10-2022-0115802 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Information Disclosure Statement
While considering applicant’s information disclosure statement, examiner observed that the Publication number for the reference by Rabkin was incorrect. The correct publication number (US Pub 20160149004) was added to the IDS.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin et al. (US Pub 20230164997) hereinafter referred to as Rabkin, in view of Choi et al., IEEE Transactions on Electron Devices, Vol. 66, No. 11 (November 2019), hereinafter referred to as Choi.
Regarding claim 1, Rabkin teaches a semiconductor device (Rabkin, 700, Fig. 14A, para. 46) comprising: a plurality of gate electrodes (Rabkin 46, Fig. 14A, para. 112) spaced apart from each other in a vertical direction on a substrate (Rabkin 9 and 10, Fig. 14A, para. 44); a plurality of channel structures (Rabkin 55, Fig. 14A, para. 96) respectively penetrating the plurality of gate electrodes and extending in the vertical direction, and each including a channel layer having a stacked structure of a first oxide semiconductor channel layer (Rabkin, 60, Fig. 6, para 83, 90) and a second oxide semiconductor channel layer (Rabkin, 621, Fig 6, para 84), and a gate insulating layer (Rabkin, 150, Figs. 6, 14A, para. 47) disposed between the channel layer and each of the plurality of gate electrodes; and a plurality of bit lines disposed on the plurality of channel structures and respectively connected to the plurality of channel structures (Rabkin, 98, Fig. 14A, para. 122), wherein the gate insulating layer, the first oxide semiconductor channel layer, and the second oxide semiconductor channel layer are sequentially disposed (Rabkin, Fig. 6).
Rabkin does not teach that the two semiconductor oxide layers have different conductivities.
However, Choi teaches an IP structure for a memory transistor that uses an IGZO element (n conductivity) and a p-doped filler (Choi, section II). Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the memory transistor of Rabkin with the IP structure of Choi to create a p-n junction, thereby greatly reducing the leakage current (Choi, section II).
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Regarding claim 2, modified Rabkin teaches the semiconductor device as claimed in claim 1, wherein: the first oxide semiconductor channel layer has an n-type conductivity (Choi, section II) and has a first thickness on the gate insulating layer (Rabkin, 60, Fig. 6),
and the second oxide semiconductor channel layer has a p-type conductivity (Choi, section II) and has a second thickness on the gate insulating layer (Rabkin, 621, Fig. 6).
Regarding claim 3, modified Rabkin teaches the semiconductor device as claimed in claim 2, wherein the first thickness is greater than the second thickness (Rabkin, 60, 621, Fig. 6, shows 60 has a greater thickness than 621).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Rabkin and Choi as applied to claim 1 above, and further in view of Cho et al. (US Pub 20210217473), hereinafter referred to as Cho.
Regarding claim 8, modified Rabkin teaches the semiconductor device as claimed in claim 1, but does not teach wherein, a bandgap of one of the first oxide semiconductor channel layer and the second oxide semiconductor channel layer having an n-type conductivity has a greater value than that of a bandgap of the other having a p-type conductivity.
However, Cho teaches a semiconductor layer (Cho, 522, Fig. 6A, para. 95) made of indium gallium zinc oxide (IGZO) and a resistance change layer (Cho, 523, Fig. 6A,para. 97) made of copper oxide.
Therefore it would have been obvious to one having ordinary skill in the art to combine the semiconductor device of Rabkin and Choi with the materials of Cho to create a first and second oxide semiconductor channel where the first oxide semiconductor channel layer has an n-type conductivity and the second oxide semiconductor channel layer has a p-type conductivity and the bandgap of the first oxide semiconductor channel layer has a greater value than the bandgap of the second oxide semiconductor channel layer. This would help increase the high density and low power characteristics of the device (Cho, para. 04).
Examiner’s note: These materials are selected from among those cited in claim 18, therefore the band gap requirement inherited by claim 18 via claim 9, which has the same band gap requirements applied here has been met.
Claims 9-11, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin, Choi and Cho.
Regarding claim 9, Rabkin teaches a semiconductor device (Rabkin, 700, Fig. 14A, para. 46) comprising: a gate stack including a plurality of gate electrodes (Rabkin, 46, Fig. 14A, para 112) and a plurality of insulating layers (Rabkin, 32, Fig. 14A, para. 51) alternately stacked on a substrate (Rabkin, 10, Fig 14A, para. 44);
a plurality of channel structures (Rabkin, 55, Fig. 14A, para 47) respectively filling a plurality of channel holes penetrating the gate stack;
and a plurality of bit lines ( Rabkin, 98, Fig. 14A, para. 122) disposed on the plurality of channel structures and respectively connected to the plurality of channel structures,
wherein each of the plurality of channel structures comprises a gate insulating layer (Rabkin, 150, Fig. 14A, para 47) including a blocking dielectric layer (Rabkin, 156, Fig. 6, para. 47), a charge storage layer (Rabkin, 154, Fig. 6, para 47), and a tunneling dielectric layer (Rabkin, 152, Fig. 6, para. 47) conformally and sequentially disposed on a sidewall of each of the plurality of channel holes;
and a channel layer having a stacked structure of a first oxide semiconductor channel layer and a second oxide semiconductor channel layer on the gate insulating layer.
Rabkin does not teach wherein the first oxide semiconductor channel layer has an n-type conductivity and the second oxide semiconductor channel layer has a p-type conductivity, nor does Rabkin teach, wherein a band gap of the first oxide semiconductor channel layer has a greater value than that of a band gap of the second oxide semiconductor channel layer.
However, Choi teaches an IP structure for a memory transistor that uses an IGZO element (n conductivity) and a p-doped filler (Choi, section II).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the memory transistor of Rabkin with the IP structure of Choi to create a p-n junction, thereby greatly reducing the leakage current (Choi, section II).
Further, Cho teaches a semiconductor layer (Cho, 522, Fig. 6A, para. 95) made of indium gallium zinc oxide (IGZO) and a resistance change layer (Cho, 523, Fig. 6A,para. 97) made of copper oxide.
Therefore it would have been obvious to one having ordinary skill in the art to combine the semiconductor device of Rabkin and Choi with the materials of Cho to create a first and second oxide semiconductor channel where the first oxide semiconductor channel layer has an n-type conductivity and the second oxide semiconductor channel layer has a p-type conductivity and the bandgap of the first oxide semiconductor channel layer has a greater value than the bandgap of the second oxide semiconductor channel layer. This would help increase the high density and low power characteristics of the device (Cho, para. 04).
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Regarding claim 10, modified Rabkin teaches the semiconductor device as claimed in claim 9, wherein each of the plurality of channel structures further includes: a buried insulating layer filling a space defined by the channel layer (Rabkin, 62, Fig. 14A, para. 85); and a conductive plug contacting the channel layer and the buried insulating layer and filling an upper side of each of the plurality of channel holes (Rabkin 63, Fig. 14A, para. 91).
Regarding claim 11, modified Rabkin teaches the semiconductor device as claimed in claim 10, wherein the first oxide semiconductor channel layer (Rabkin, 60, Fig. 6) conformally covers the gate insulating layer (Rabkin, 150, Fig. 6) covering a sidewall of each of the plurality of channel holes and a bottom portion of each of the plurality of channel holes to a first thickness and the second oxide semiconductor channel layer (Rabkin, 621, Fig. 6) conformally covers the first oxide semiconductor channel layer to a second thickness equal to or smaller than the first thickness (Rabkin, Fig. 6, 621 is thinner than 60).
Regarding claim 16, modified Rabkin teaches the semiconductor device as claimed in claim 9, wherein the first oxide semiconductor channel layer includes at least one oxide semiconductor material of a quaternary oxide semiconductor material including three different metal atoms or a quinary oxide semiconductor material including four different metal atoms, (Cho, para. 95), and the second oxide semiconductor channel layer includes a binary oxide semiconductor material including one metal element (Cho, para. 97).
Regarding claim 18, modified Rabkin teaches the semiconductor device as claimed in claim 9, wherein the first oxide semiconductor channel layer includes at least one of indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO) (Cho, 522, Fig. 6A, para 95, recites IGZO),and the second oxide semiconductor channel layer includes at least one of tin oxide (SnO), tellurium oxide (TeO), copper oxide (CuO), bismuth oxide (BiO), or nickel oxide (NiO) (Cho, 523, Fig. 6A, para. 97, recites copper oxide).
Regarding claim 19, Rabkin teaches an electronic system comprising: a main substrate (Rabkin, 9, 10, Fig. 14A, para. 44);
a semiconductor device on the main substrate (Rabkin, 700, Fig. 14A, para. 46);
wherein the semiconductor device includes:
a plurality of gate electrodes spaced apart from each other in a vertical direction on the main substrate (Rabkin, 46, Fig. 14A, para. 112);
a plurality of channel structures respectively penetrating the plurality of gate electrodes and extending in the vertical direction (Rabkin, 58, Fig 14A, para. 132);
a plurality of bit lines disposed on the plurality of channel structures and respectively connected to the plurality of channel structures (Rabkin, 98, Fig. 14A, para. 122);
a peripheral circuit electrically connected to the plurality of gate electrodes and the plurality of bit lines (Rabkin, para. 46);
wherein each of the plurality of channel structures comprises a channel layer having a stacked structure of a first oxide semiconductor channel layer (Rabkin, 60, Fig. 6, paras. 83, 90) and a second oxide semiconductor channel layer (Rabkin, 621, Fig. 6, 84),
and a gate insulating layer (Rabkin, 150, Fig. 6, 14A, para. 74) disposed between the channel layer and each of the plurality of gate electrodes,
and the gate insulating layer, the first oxide semiconductor channel layer, and the second oxide semiconductor channel layer are sequentially disposed (Rabkin, Fig. 6A).
Rabkin does not teach a controller electrically connected to the semiconductor device on the main substrate, and an input/output pad electrically connected to the peripheral circuit, or wherein each of the plurality of channel structures comprises a channel layer having a stacked structure of a first oxide semiconductor channel layer and a second oxide semiconductor channel layer having different conductivities.
However, Cho teaches a memory controller (Cho, 100, Fig. 1, para. 69), and an input/output pad electrically connected to the peripheral circuit (Cho, 240, Fig. 2, para. 78)
Therefore it would have been obvious to combine the semiconductor device of Rabkin with the memory controller and input/output pad of Cho in order to equip the device with input/output and read/write capability as well as transforming the control logic into special purpose processing circuitry (Cho, para. 69, 78,-80) .
Further, Choi teaches Choi teaches an IP structure for a memory transistor that uses an IGZO element (n conductivity) and a p-doped filler (Choi, section II). Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the memory transistor of Rabkin and Cho with the IP structure of Choi to create a p-n junction, thereby greatly reducing the leakage current (Choi, section II).
Regarding claim 20, modified Rabkin teaches he electronic system as claimed in claim 19, wherein the first oxide semiconductor channel layer has an n-type conductivity (Choi, section II) and has a first thickness on the gate insulating layer (Rabkin, 60, Fig. 6),
and the second oxide semiconductor channel layer has a p-type conductivity (Choi, section II) and has a second thickness smaller than the first thickness on the gate insulating layer (Rabkin, 621, Fig. 6).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Rabkin, Choi and Cho as applied to claim 16 above, and further in view of Yang et al. (US Pub 20220037253).
Regarding claim 17, modified Rabkin teaches the semiconductor device as claimed in claim 16, but does not teach wherein the second oxide semiconductor channel layer includes a binary oxide semiconductor material including one same metal element among metal elements included in an oxide semiconductor material constituting the first oxide semiconductor channel layer.
However, Yang teaches a channel blanket layer (Yang, 424A, Fig. 13) which can include a quinary oxide containing titanium (Yang, para. 32). Yang additionally teaches a cap blanket layer (Yang, 426a, Fig. 13) which can comprise titanium oxide.
Therefore it would have been obvious to one having ordinary skill in the art to have combined the semiconductor device of Rabkin, Choi and Cho with the matching metals of Yang to balance the requirements of reliability with the requirements of etching performance (Yang, para. 33)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Imai et al. (US Pub. 20230345716) -Teaches a semiconductor memory device with two semiconductor channel layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 7:30-5:00.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893