DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al (US Pub No. 20190148439).
With respect to claim 1, Shin et al discloses a first substrate (110,Fig.2A) comprising a first surface (top) and a second surface (bottom) opposite to the first surface, wherein the first substrate includes a sensor array region (APR), a pad region (right of 150), and a connection region between the sensor array region and the pad region (150 to APR); a first isolation trench in the first substrate at the sensor array region (124T), the first isolation trench defining a plurality of unit pixels (Fig.2A); a second isolation trench in the first substrate at the connection region (150) ; a third isolation trench in the first substrate at the pad region (160); a first film on an inner surface of the first isolation trench (126), wherein the first film has a top surface (top surface inside the trench) and a bottom surface opposite to the top surface of the first film (bottom of 126); a second film on an inner surface of the second isolation trench (156), wherein the second film has a top surface (Fig.2A) and a bottom surface opposite to the top surface of the second film (Fig.2A); and a third film on an inner surface of the third isolation trench (126), wherein the third film has a top surface (Fig.2A) and a bottom surface opposite to the top surface of the third film (Fig.2A), wherein the top surfaces of the first, second and third films are spaced apart from the second surface (Fig.2A), wherein the first isolation trench has a first width in a first direction at the bottom surface of the first film (in the x direction near the bottom of the trench), wherein the second isolation trench has a second width in the first direction at the bottom surface of the second film (Fig.2A), wherein the third isolation trench has a third width in the first direction at the bottom surface of the third film (Fig.2A), wherein the third width is different from the second width (Fig.2A) and the second width is different from the first width (Fig.2A), wherein the first direction is parallel to the first surface of the first substrate (Fig.2A), and wherein the image sensor is configured to receive light at the first surface (Fig.2A).
With respect to claim 2, Shin et al discloses wherein the second width is greater than the first width (Fig.2A).
With respect to claim 4, Shin et al discloses further comprises a first filling film (124, silicon oxide) filling the first isolation trench on the first film.
Claim(s) 10-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al (US Pub No. 2013032875).
With respect to claim 10, Park et al discloses an image sensor (Fig.6) comprising:
a first substrate (100a) comprising a first surface (top surface) and a second surface (bottom surface) opposite to the first surface (FIg.6), wherein the first substrate includes a sensor array region (106, pixel region), an edge region (left of 114 in the pad region), a pad region (the rest of the pad region till peripheral circuit ) between the sensor array region and the edge region (FIg.2A), and a connection region (peripheral circuit region) between the sensor array region and the pad region (FIg.6); a first isolation trench in the first substrate at the sensor array region (120d), the first isolation trench defining a plurality of unit pixels (Fig.6); a second isolation trench in the first substrate at the connection region (120c); a third isolation trench in the first substrate at the pad region (114); a fourth isolation trench in the first substrate at the edge region (115a); a first film on an inner surface of the first isolation trench (Fig.6), wherein the first film has a top surface (at top of the trench) and a bottom surface (at the bottom of the trench) opposite to the top surface of the first film; a second film (Fig.6) on an inner surface of the second isolation trench (Fig.6), wherein the second film has a top surface (in the top portion of the trench) and a bottom surface (at the bottom surface of the trench) opposite to the top surface of the second film; and a third film on an inner surface of the third isolation trench (Fig.6), wherein the third film has a top surface (at the top surface of the trench) and a bottom surface opposite to the top surface of the third film (at the bottom surface); and
a fourth film on an inner surface of the fourth isolation trench (Fig.6), wherein the fourth film has a top surface (Fig.6) and a bottom surface opposite to the top surface of the fourth film (Fig.6), wherein the top surfaces of the first, second, third film, and fourth films are spaced apart from the second surface (Fig.6), wherein the first isolation trench has a first width (Fig.6) in a first direction (in the x direction) at the bottom surface of the first film,
wherein the second isolation trench has a second width (Fig.6) in the first direction at the bottom surface of the second film (Fig.6), wherein the third isolation trench has a third width (Fig.6) in the first direction at the bottom surface of the third film, wherein the fourth isolation trench has a fourth width (Fig.6) in the first direction at the bottom surface of the fourth film (Fig.6),
wherein the third width is greater than the first width and the fourth width (Fig.6), wherein the second width is different from the third width (Fig.6), wherein the first direction is parallel to the first surface of the first substrate (the x direction is parallel to the surface), and wherein the image sensor is configured to receive light at the first surface (Fig.6).
With respect to claim 11, Park et al discloses wherein the first, second, and third isolation trenches extend from the second surface to the first surface (Fig.6).
With respect to claim 12, Park et al discloses wherein the first, second, and third isolation trenches penetrate the first substrate (Fig.6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (Us Pub No. 20190148439), in view of Lee (US Pub No. 20190148427).
With respect to claim 3, Shin et al does not explicitly disclose wherein the third with is greater than the first width. On the other hand, Lee discloses wherein the third width (bottom of the 27 on the left, Fig.2) is greater than the first width (29). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Shin et al according to the teachings of the Lee such that the third width is greater than the first width in order to increase the pixel density, thereby improving the picture quality.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (Us Pub No. 20190148439), in view of Ohura (US Pub No. 20210005651).
With respect to claim 5, Shin et al does not disclose wherein the first filling film includes polysilicon. On the other hand, Ohura discloses that the first filling film includes polysilicon (86,Fig.3). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Shin et al according to the teachings of the OHURA such that the filing is made out of polysilicon since it is abundant and cheap in the industry and would cut the cost of the device.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (Us Pub No. 20190148439), in view of Lee et al (US Pub No. 20090140365).
With respect to claim 6, Shin et al does not explicitly disclose wherein the first and second isolation trenches penetrate the first substrate, and wherein the first and second isolation trenches extend from the second surface to the first surface. On the other hand, Lee et al discloses wherein the isolation trenches (210, Fig.15) penetrate the first substrate (110,105), and wherein the isolation trenches extend from the second surface to the first surface (Fig.16). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Shin et al according to the teachings of the Lee et al such that the first and second isolation trenches penetrate the first substrate from first surface to the second surface in order to better isolate the pixels from each other, thereby improving the performance of the device.
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (Us Pub No. 20190148439), in view of Park (US Pub No.20150255495).
With respect to claim 7, Shin et al discloses a second substrate (186) comprising a third surface (top surface) facing the second surface (Fig.2A), and a fourth surface opposite to the third surface (Bottom surface); a plurality of wirings (130) between the second surface and the third surface (Fig.2A); a first through via at the connection region (140) connected to the wiring region (Fig.2A). However, Shin et al does not explicitly disclose and a second through via spaced apart from the first through via at the connection region, and wherein each of the first through via and second through via is connected to at least a part of the plurality of wirings. On the other hand, Park discloses first (140,Fig.2) and second (150,Fig.2) vias connected to the wiring (161,160), and first and second vias spaced apart from the first through via at the connection region (Fig.2), and wherein each of the first through via and second through via is connected to at least a part of the plurality of wirings (Fig.2). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Shin et al according to the teachings of Pak such that there two conductive vias connected to the wiring in order to increase process signals capacity, thereby increasing speed of the device.
With respect to claim 8, Shin et al discloses wherein the first through via has a tapered shape (Fig.2A).
With respect to claim 9, Shin et al in view of Park discloses wherein the second isolation trench (150) extends from the second surface to the first surface (Fig.2).
Claim(s) 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (Us Pub No. 2013032875).
With respect to claim 13, Park et al discloses wherein the fourth width is different from the first width (fourth trench looks wider than the first trench, Fig.6). Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
With respect to claim 14, Park et al discloses wherein the second width is greater than the first width (Fig.6). Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
With respect to claim 15, Park et al discloses wherein the fourth width is different from the first width (Fig.6). Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
With respect to claim 16, Park et al does not explicitly disclose wherein the first width is between 100 nm to 300 nm. Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it would have been obvious to one of ordinary skill in the art at the time of the invention to have trenches near 100nm width in order to decrease the size of the device, thereby cutting the cost.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (Us Pub No. 2013032875), in view of ohura (US Pub No. 20210005651).
With respect to claim 17, Park et al does not explicitly disclose further comprising a first filling film filling the first isolation trench on the first film. On the other hand, Ohura discloses a filling film in the isolation trench structure. On the other hand, Ohura discloses a first filling film (86,Fig.3) filling the isolation trench (82) on the first film (85). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Park et al according to the teachings of the OHURA such that filling like polysilicon is used to fill the isolation trench, since it is among the cheapest material in the industry thereby making the device cost effective.
With respect to claim 18, Ohura discloses wherein the first filling film includes polysilicon (Para 91).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (Us Pub No. 2013032875), in view of Park (US Pub No. 20150255495).
With respect to claim 19, Park et al discloses a second substrate (112) comprising a third surface facing the second surface (top surface), and a fourth surface (bottom surface) opposite to the third surface (Fig.6); a plurality of wirings (108) between the second surface and the third surface (Fig.6); a first through via at the connection region (126). However, Park does not explicitly disclose a second through via spaced apart from the first through via at the connection region, and wherein each of the first through via and second through via is connected to at least a part of the plurality of wirings. On the other hand, Park discloses first (140,Fig.2) and second (150,Fig.2) vias connected to the wiring (161,160), and first and second vias spaced apart from the first through via at the connection region (Fig.2), and wherein each of the first through via and second through via is connected to at least a part of the plurality of wirings (Fig.2). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Shin et al according to the teachings of Pak such that there two conductive vias connected to the wiring in order to increase process signals capacity, thereby increasing speed of the device.
Conclusion
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/ALI NARAGHI/Primary Examiner, Art Unit 2817