Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/13/2023 and 4/8/2026 was filed before the mailing date of the Non-final rejection on 4/13/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The formal drawings filed on 9/13/2023 have been approved by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “NON-VOLATILE VERTICAL MEMORY DEVICE”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 9, 11, 12, and 15--20 are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Shin et al. (US 2022/0181284).
With respect to Claim 1, Zhang teaches a peripheral circuit structure 207 and cell array structure 212, wherein the peripheral circuit structure comprises a circuit substrate 202. A peripheral circuit 204 on the circuit substrate. A first insulating layer 206 covering the circuit substrate 202 and the peripheral circuit. A first bonding pad 233 disposed on the first insulating layer, wherein the cell array structure comprises an insulating structure 214 having a first surface and a second surface opposing the first surface. A conductive plate 211 on the first surface of the insulating structure 214. A memory cell array on the conductive plate. A second insulating layer (i.e. in 212) covering the first surface of the insulating structure, the conductive plate, and the memory cell array. A second bonding pad 231 disposed on the second insulating layer. A first wiring line 221 and a second wiring line 223 spaced apart from each other on the second surface of the insulating structure 214. A conductive via 241 passing through the insulating structure and electrically connecting the conductive plate 211 to the first wiring line 221. A contact structure 215 electrically connecting the first wiring line to the second bonding pad 231. The first bonding pad 233 is in contact with the second bonding pad 233 (see paragraphs 41-58 and 89-94; Figs. 1C, 2, and 3J-3N).
With respect to Claim 2, Zhang teaches in plan view, the first wiring line 221 has a first length in a first horizontal direction and overlaps an edge of the conductive plate 211. The second wiring line 223 has a second length in the first horizontal direction and overlaps the conductive plate from one side of the second wiring line to another side of the second wiring line. The second length of the second wiring line 223 is longer than the first length of the first wiring line 221 (see Figs. 1C, 2, and 3J-3N).
With respect to Claim 5, Zhang teaches the contact structure includes a first contact plug 241 passing through the insulating structure. A second contact plug passing through the second insulating layer. The first contact plug 241 is tapered and has a width narrowing in a vertical direction toward the circuit substrate. The second contact plug is tapered and has a width widening in the vertical direction toward the circuit substrate (see Figs. 1C, 2, and 3J-3N).
With respect to Claim 6, Zhang teaches a first height of the first contact plug 241 in the vertical direction is less than a second height of the second contact plug 215in the vertical direction (see Figs. 1C, 2, and 3J-3N).
With respect to Claim 9, Zhang teaches the conductive plate 223 corresponds to a common source line. The peripheral circuit includes a common source line (CSL) driver. The common source line is electrically connected to the CSL driver by bypassing the first wiring line and the contact structure (see paragraph 52; Figs. 1C, 2, and 3J-3N).
With respect to Claims 11 and 16, Zhang teaches a peripheral circuit structure 202, 204-206 including a circuit substrate 202, a peripheral circuit 204 on the circuit substrate. A first insulating layer 205 covering the peripheral circuit. A first bonding pad 233 disposed on the first insulating layer 205. A first cell array structure 203 including a first conductive plate 211, a first memory cell array 212 below the first conductive plate. A second insulating layer 213 covering the first memory cell array 212. A second bonding pad 231 below the second insulating layer. A first conductive via 241 on the first conductive plate 211. A third bonding pad 219 connected to the first conductive via 241. A first contact structure 215 passing through the second insulating layer to connect the second bonding pad 231 to the third bonding pad 219. A second cell array structure (i.e. another structure 200) including a second conductive plate 211, a second memory cell array below the second conductive plate. A third insulating layer 213 covering the second memory cell array 212, a fourth bonding pad 231 below the third insulating layer. A second conductive via 241 on the second conductive plate. A first wiring line 223 connected to the second conductive via 241, and a second contact structure 215 passing through the third insulating layer to connect the fourth bonding pad to the first wiring line, wherein the first bonding pad 233 is in contact with the second bonding pad 231. The third bonding pad is in contact with the fourth bonding pad (see paragraphs 41-58 and 89-99; Figs. 1C, 2, 3J-3N, and 6).
With respect to Claim 12, Zhang teaches the fourth bonding pad 231 comprises a plurality of fourth bonding pads. The IC device further comprises an extended wiring line 223 disposed in the third insulating layer of the second cell array structure and electrically connecting the plurality of fourth bonding pads 223. The first conductive plate 211 of the first cell array structure is electrically connected to the first contact structure a through the extended wiring line (see Figs. 2 and 6).
With respect to Claim 14, Zhang teaches a second wiring line disposed on the same vertical level in the as a vertical level of the first wiring line 223. The second wiring line overlaps the second conductive plate 211 from one side of the second wiring line to another side of the second wiring line in the first horizontal direction (see paragraph 98; Figs. 1C, 2, 3J-3N, and 6).
With respect to Claims 17\ and 20, Zhang teaches the first conductive plate and 211 the second conductive plate 211 (i.e. in the 2nd memory cell array) correspond to a common source line. The peripheral circuit includes a common source line (CSL) driver. The first conductive plate 211 is electrically connected to the CSL driver by bypassing the extended wiring line and the first contact structure. The second conductive plate 211 is electrically connected to the CSL driver by bypassing the first wiring line and the second contact structure (see paragraph 98; Figs. 1C, 2, 3J-3N, and 6).
With respect to Claim 18, Zhang teaches the first contact structure 215 in the first memory cell array is located outside the first memory cell array 212. The second contact structure 215 in the second memory cell array is located outside the second memory cell array (see paragraph 98; Figs. 1C, 2, 3J-3N, and 6).
With respect to Claim 19, Zhang teaches the first conductive via 241 is tapered and has a width narrowing in a vertical direction toward the circuit substrate. Each of the first contact structure 215 and the second contact structure 215 is tapered and has a
width widening in the vertical direction toward the circuit substrate (see paragraph 98; Figs. 1C, 2, 3J-3N, and 6).
Allowable Subject Matter
8. Claims 3, 4, 7, 8, 10, 13, 14 are objected to as being dependent upon a rejected
base claim, but would be allowable if rewritten in independent form including all of the
limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record does not teaches or suggest the combination the second wiring line comprises a plurality of second wiring lines. In a plan view, the plurality of second wiring lines are respectively disposed on both sides of the first wiring line in a second horizontal direction perpendicular to the first horizontal direction in claim 3.
In plan view, a length of an overlap region in which the conductive plate overlaps the first wiring line in the first horizontal direction is about 5 µm or less. The conductive via is located only in the overlap region in claim 4.
An input/output (1/O) pad located at an end of the second wiring line,
wherein a bonding wire is connected to the I/O pad to perform a power connection
function and/or a ground connection function in claim 7.
The conductive plate includes a stack structure of a polysilicon layer, a barrier metal layer, and a metal layer in claim 10.
The first wiring line has an overlap region overlapping an edge of the second conductive plate in a first horizontal direction. The second conductive via is disposed only in the overlap region in claim 13.
The prior art made of record and not relied upon is cited primarily to show the
product of the instant invention.
Conclusion
9. Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/April 13, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
Prosecution Insights