Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 is objected for claim language “….. a binding reinforcement layer on surfaces of each of the plurality of connection structures and at least a portion of the semiconductor chip…..”. Applicant needs to amend the claim if binding reinforcement layer is on at least a portion of the semiconductor chip.
Claim 18 is objected for claim language
“……the plurality of connection structures being on the semiconductor chip… “….
……….
a binding reinforcement layer on an upper surface of the first rewiring structure, side surfaces of each of the plurality of connection structures, side surfaces of the under-fill layer, at least a portion of side surfaces of the semiconductor chip, and an upper surface of the semiconductor chip, the binding reinforcement layer comprising an insulating material; and “an encapsulation member filling a space between the first rewiring structure and the second rewiring structure, covering the plurality of connection structures and the semiconductor chip, and being spaced apart from the first rewiring structure, the semiconductor chip, and each of the plurality of connection structures, with the binding reinforcement layer between the encapsulation member and the first rewiring structure, the semiconductor chip, and each of the plurality of connection structures”.
According to specs, drawings and other claims “…the plurality of connection structures being adjacent to the semiconductor chip “. Applicant needs to amend the claim to clarify what is being covered by the binding reinforcement layer and the encapsulation member.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2022/0020676, hereinafter Yu) in view of Choi et al. (US 2012/0211885, hereinafter Choi).
With respect to claim 1, Yu discloses a semiconductor package (Fig. 7) comprising:
a first wiring structure (100) comprising:
a plurality of first wiring patterns (120) respectively comprising a plurality of first lower surface connection pads (124) and a plurality of first upper surface connection pads (122); and a first base insulating layer (110) surrounding the plurality of first wiring patterns (Fig. 7); a second wiring structure (200) comprising: a plurality of second wiring patterns (220) respectively comprising a plurality of second lower surface connection pads (224) and a plurality of second upper surface connection pads (222); and a second base insulating layer (210) surrounding the plurality of second wiring patterns (Fig. 7); a semiconductor chip (10) between the first wiring structure and the second wiring structure (10 is between 100 & 200); an encapsulation member (170) filling a space between the first wiring structure and the second wiring structure and surrounding the semiconductor chip (Fig. 7); a plurality of connection structures (166/168) penetrating the encapsulation member (166/168 penetrates through 170) and connecting some of the plurality of first upper surface connection pads to the plurality of second lower surface connection pads (166/168 connects 122 to 224), the plurality of connection structures being adjacent to the semiconductor chip (Fig. 7).
Yu does not explicitly disclose a binding reinforcement layer on side surfaces of each of the plurality of connections structures and at least a portion of side surfaces of the semiconductor chip.
In an analogous art, Choi discloses a binding reinforcement layer (150 & 781 of Fig. 62) on side surfaces of each of the plurality of connections structures (770) and at least a portion of side surfaces of the semiconductor chip (130). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yu’s device by having Choi’s disclosure in order to provide mechanical reinforcement and protect the connections of a semiconductor device.
With respect to claim 2, Yu discloses wherein the encapsulation member is spaced apart from the semiconductor chip (Fig. 7 - 170 is spaced apart from chip 10 on the sides – layer 50 is in between of 170 and 10).
Yu does not explicitly disclose that the encapsulation member is spaced apart from each of the plurality of connection structures.
In an analogous art, Choi discloses that the encapsulation member (170 a) is spaced apart from each of the plurality of connection structures (Fig. 62 – there is a layer 150 between 170a and connecting structures 770).
Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu’s device by having Choi’s disclosure in order to protect different components of a semiconductor device during processing.
With respect to claim 3, Yu does not explicitly disclose wherein the binding reinforcement layer is between the first wiring structure and the encapsulation member, between the semiconductor chip and the encapsulation member, and between the plurality of connection structures and the encapsulation member.
In an analogous art, Choi discloses wherein the binding reinforcement layer is between the first wiring structure and the encapsulation member (Fig. 46 – 150 is between 126 and top part o of 170), between the semiconductor chip and the encapsulation member (150 is between 130 and 170), and between the plurality of connection structures and the encapsulation member (150 is between 260 and 170). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu’s device by having Choi’s disclosure in order to protect different components of a semiconductor device during processing.
With respect to claim 4, Yu discloses wherein the encapsulation member (170) is spaced apart from the first base insulating layer (Fig. 7 - there is a layer between 110 and 170)) and is in contact with the second base insulating layer (170 is indirectly in contact with 210).
Yu does not explicitly disclose wherein the binding reinforcement layer is between the encapsulation member and the first base insulating layer.
In an analogous art, Choi discloses wherein the binding reinforcement layer (150 of fig. 46) is between the encapsulation member (top part of 170) and the first base insulating layer (121).
Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu’s device by having Choi’s disclosure in order to protect different components of a semiconductor device during processing.
With respect to claim 5, Yu discloses wherein the semiconductor chip comprises: a plurality of chip pads (16’s of Fig. 7); and a plurality of chip connection members (18’s) between the plurality of chip pads and some of the plurality of first upper surface connection pads (18’s are between 16’s and 122’s).
With respect to claim 6, Yu discloses an under-fill layer (50 of Fig. 7) between the semiconductor chip and the first wiring structure (50 is between 100 and 10), and the under-fill layer surrounding the plurality of chip connection members (50 surrounds 18’s).
Yu does not explicitly disclose wherein the binding reinforcement layer is on side surfaces of the plurality of connection structures, an upper surface of the first wiring structure, side surfaces of the under-fill layer, side surfaces of the semiconductor chip, and an upper surface of the semiconductor chip.
In an analogous art, Choi discloses wherein the binding reinforcement layer (150&781 of Fig. 62) is on side surfaces of the plurality of connection structures (150 is on side surfaces of 770’s) , an upper surface of the first wiring structure (150 is on 126), side surfaces of the under-fill layer (Para 0121; 0123-0124; 0133-0134), side surfaces of the semiconductor chip (150 is on sides of 130), and an upper surface of the semiconductor chip (781 is on the upper surface of 130).
Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu’s device by having Choi’s disclosure in order to protect different components of a semiconductor device during processing.
Claims 9, 11-15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yu/Choi in view of Zhang (WO 2021/062742, hereinafter Zhang).
With respect to claim 9, Yu/Choi discloses the semiconductor package of claim 1.
Yu/Choi does not explicitly disclose wherein each of the first wiring structure and the second wiring structure comprises a rewiring structure.
In an analogous art, Zhang discloses wherein each of the first wiring structure (page 18, para 01 - rewiring layer RDL1) and the second wiring structure comprises a rewiring structure (page 19, para 02 – rewiring layer RDL2). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu/Choi’s device by having Zhang’s disclosure in order to reduce package size and improve electrical performance by allowing flexible, high-speed connections.
With respect to claim 11, Yu discloses a semiconductor package (Fig. 7) comprising: a first wiring structure (100) comprising: a plurality of first wiring patterns (120) respectively comprising a plurality of first lower surface connection pads (124) and a plurality of first upper surface connection pads (122); and a first wiring insulating layer (110) surrounding the plurality of first wiring patterns (Fig. 7); a second wiring structure (200) comprising: a plurality of second wiring patterns (220) respectively comprising a plurality of second lower surface connection pads (224) and a plurality of second upper surface connection pads (222); and a second wiring insulating layer (210) surrounding the plurality of second wiring patterns (Fig. 7); a semiconductor chip (10) between the first wiring structure and the second wiring structure (10 is between 100 & 200), the semiconductor chip comprising a plurality of chip pads (16’s); a plurality of connection structures (166/168) respectively connecting the plurality of first upper surface connection pads to the plurality of second lower surface connection pads (166/168 connects 122 to 224), the plurality of connection structures being adjacent to the semiconductor chip (Fig. 7); a plurality of chip connection members (18’s) between some of the plurality of first upper surface connection pads and the plurality of chip pads (18’s are between 16’s and 122’s); and an encapsulation member (170) surrounding the plurality of connection structures and the semiconductor chip (170 surrounds 166/168 and 10), filling a space between the first wiring structure and the second wiring structure (170 is between 100 and 200), and being spaced apart from the semiconductor chip (Fig. 7 - 170 is spaced apart from chip 10 on the sides – layer 50 is in between of 170 and 10).
Yu does not explicitly disclose a binding reinforcement layer on side surfaces of each of the plurality of connection structures and at least a portion of the semiconductor chip; the encapsulation member is spaced apart from each of the plurality of connection structures; the binding reinforcement layer being between the encapsulation member and each of the plurality of connection structures.
In an analogous art, Choi discloses a binding reinforcement layer (150 & 781 of Fig. 62) on side surfaces of each of the plurality of connections structures (770) and at least a portion of the semiconductor chip (130); the encapsulation member (170 a) is spaced apart from each of the plurality of connection structures (Fig. 62 – there is a layer 150 between 170a and connecting structures 770); the binding reinforcement layer being between the encapsulation member and each of the plurality of connection structures (150 is between 170 and 770).
Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu’s device by having Choi’s disclosure in order to protect different components of a semiconductor device during processing.
Yu/Choi does not explicitly disclose wherein each of the first wiring structure and the second wiring structure comprises a rewiring structure.
In an analogous art, Zhang discloses wherein each of the first wiring structure (page 18, para 01 - rewiring layer RDL1) and the second wiring structure comprises a rewiring structure (page 19, para 02 – rewiring layer RDL2). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu/Choi’s device by having Zhang’s disclosure in order to reduce package size and improve electrical performance by allowing flexible, high-speed connections.
With respect to claim 18, Yu discloses a semiconductor package (Fig. 7) comprising: a first wiring structure (100) comprising: a plurality of first wiring patterns (120) respectively comprising a plurality of first lower surface connection pads (124) and a plurality of first upper surface connection pads (122); and a first wiring insulating layer (110) surrounding the plurality of first wiring patterns (Fig. 7);
a semiconductor chip (10) on the first wiring structure and comprising a plurality of chip pads (16’s); a second wiring structure (200) comprising: a plurality of second wiring patterns (220) on the semiconductor chip and the first wiring structure, the
plurality of second wiring patterns respectively comprising a plurality of second lower surface connection pads (224) and a plurality of second upper surface connection pads (222); and a second wiring insulating layer (210) surrounding the plurality of second wiring patterns (Fig. 7);
a plurality of connection structures (166/168) respectively connecting some of the plurality of first upper surface connection pads to the plurality of second lower surface connection pads (166/168 connects 122 to 224), the plurality of connection structures being on the semiconductor chip (Fig. 7);
a plurality of chip connection members (18’s) between some of the plurality of first upper surface connection pads and the plurality of chip pads (18’s are between 16’s and 122’s);
an under-fill layer (50) between the semiconductor chip and the first rewiring structure (Fig. 7), the under-fill layer surrounding the plurality of chip connection members (50 surrounds 18’s); and an encapsulation member (170) filling a space between the first rewiring structure and the second rewiring structure (Fig. 7), covering the plurality of connection structures and the semiconductor chip (Fig. 7), and being spaced apart from the first wiring structure (there is a layer between 100 and 170), the semiconductor chip (there is a layer 50 between 10 and 170),
Yu does not explicitly disclose that the plurality of chip connection members respectively comprising a under bump metal (UBM) layer and a conductive cap on each of the plurality of chip pads , the conductive cap covering the UBM layer; a binding reinforcement layer on an upper surface of the first rewiring structure, side surfaces of each of the plurality of connection structures, side surfaces of the under-fill layer, at least a portion of side surfaces of the semiconductor chip, and an upper surface of the semiconductor chip, the binding reinforcement layer comprising an insulating material, and the encapsulation member being spaced apart from each of the plurality of connection structures, with the binding reinforcement layer between the encapsulation member and the first rewiring structure, the semiconductor chip, and each of the plurality of connection structures.
In an analogous art, Choi discloses that the plurality of chip connection members respectively comprising a under bump metal (UBM) layer and a conductive cap on each of the plurality of chip pads , the conductive cap covering the UBM layer (para 0077-0078) a binding reinforcement layer (150 & 781 of Fig. 62) on an upper surface of the first wiring structure (fig. 62), side surfaces of each of the plurality of connection structures (770), side surfaces of the under-fill layer (Para 0121; 0123-0124; 0133-0134), at least a portion of side surfaces of the semiconductor chip (150 is on sides of 130), and an upper surface of the semiconductor chip (781 is on the upper surface of 130), the binding reinforcement layer comprising an insulating material (para 0070 – 150 comprises of an insulating material); the encapsulation member (170 a) is spaced apart from each of the plurality of connection structures (Fig. 62 – there is a layer 150 between 170a and connecting structures 770); wherein the binding reinforcement layer between the encapsulation member and the first rewiring structure (Fig. 46 – 150 is between 126 and top part o of 170), the semiconductor chip (150 is between 130 and 170), and each of the plurality of connection structures (150 is between 260 and 170). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu’s device by having Choi’s disclosure in order to protect different components of a semiconductor device during processing.
Yu/Choi does not explicitly disclose wherein each of the first wiring structure and the second wiring structure comprises a rewiring structure.
In an analogous art, Zhang discloses wherein each of the first wiring structure (page 18, para 01 - rewiring layer RDL1) and the second wiring structure comprises a rewiring structure (page 19, para 02 – rewiring layer RDL2). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu/Choi’s device by having Zhang’s disclosure in order to reduce package size and improve electrical performance by allowing flexible, high-speed connections.
With respect to claim 12, Yu/Choi/Zhang discloses the semiconductor package of claim 11.
Yu does not explicitly disclose wherein the binding reinforcement layer is on an upper surface of the first wiring structure, upper surfaces of the plurality of connection structures, at least a portion of side surfaces of the semiconductor chip, and an upper surface of the semiconductor chip.
In an analogous art, Choi discloses wherein the binding reinforcement layer (150 & 781 of Fig. 62) is on an upper surface of the first wiring structure (150 & 781 is on 126), upper surfaces of the plurality of connection structures (781 is on upper surfaces of 770) , at least a portion of side surfaces of the semiconductor chip (150 is on the side of 130), and an upper surface of the semiconductor chip (781 is on 130). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu/Choi’s device by having Zhang’s disclosure in order to reduce package size and improve electrical performance by allowing flexible, high-speed connections.
With respect to claim 13, Yu discloses an under-fill layer (50 of Fig. 7) between the semiconductor chip and the first wiring structure (50 is between 100 and 10), and the under-fill layer surrounding the plurality of chip connection members (50 surrounds 18’s).
Yu does not explicitly disclose wherein the binding reinforcement layer is on side surfaces of the plurality of connection structures, an upper surface of the first wiring structure, side surfaces of the under-fill layer, at least a portion of side surfaces of the semiconductor chip, and an upper surface of the semiconductor chip.
In an analogous art, Choi discloses wherein the binding reinforcement layer (150&781 of Fig. 62) is on side surfaces of the plurality of connection structures (150 is on side surfaces of 770’s) , an upper surface of the first wiring structure (150 is on 126), side surfaces of the under-fill layer (Para 0121; 0123-0124; 0133-0134), at least a portion of side surfaces of the semiconductor chip (150 is on sides of 130), and an upper surface of the semiconductor chip (781 is on the upper surface of 130).
Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu’s device by having Choi’s disclosure in order to protect different components of a semiconductor device during processing.
With respect to claim 14, Yu/Choi/Zhang discloses the semiconductor package of claim 11.
Yu does not explicitly disclose wherein the binding reinforcement layer is on side surfaces of the plurality of connection structures, an upper surface of the first wiring structure, side surfaces of the plurality of chip connection members, a lower surface of the semiconductor chip, side surfaces of the semiconductor chip, and an upper surface of the semiconductor chip.
In an analogous art, Choi discloses wherein the binding reinforcement layer is on side surfaces of the plurality of connection structures (150 is on side surfaces of 770), an upper surface of the first wiring structure (150/781 is on 126), side surfaces of the plurality of chip connection members (150 is on side surface of 140), a lower surface of the semiconductor chip (150 is at the lower surface of 130), side surfaces of the semiconductor chip (150 is on side surfaces of 130), and an upper surface of the semiconductor chip (781 is on side surface of 130). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu’s device by having Choi’s disclosure in order to protect different components of a semiconductor device during processing.
With respect to claim 15, Yu discloses wherein the plurality of first upper surface connection pads protrude from an upper surface of the first rewiring insulating layer (Fig. 7 – 122 protrudes from 110), and wherein a lower surface of each of the plurality of second lower surface connection pads and a lower surface of the second rewiring insulating layer are coplanar (Fig. 7- 124 and 110 are coplanar).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu/Choi in view of Zhuang (CN 112397396, hereinafter Zhuang).
With respect to claim 10, Yu/Choi discloses the semiconductor package of claim 1.
Yu/Choi does not explicitly disclose wherein the first wiring structure comprises a printed circuit board, and wherein the second wiring structure comprises a rewiring structure.
In an analogous art, Zhuang discloses wherein the first wiring structure comprises a printed circuit board (page 05; last para; and page 24; last para – PCB), and wherein the second wiring structure comprises a rewiring structure (page 06; para 02-03; rewiring). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu/Choi’s device by having Zhang’s disclosure in order to reduce package size and improve electrical performance by allowing flexible, high-speed connections.
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yu/Choi/Zhang in view of Dias et al. (US 2015/0072479, hereinafter Dias).
With respect to claim 19, Yu/Choi/Zhang discloses the semiconductor package of claim 18,
Yu/Choi/Zhang does not explicitly dilcose that the binding reinforcement layer comprises silicon oxynitride (SiON).
In an analogous art, Dias discloses the semiconductor package of claim 18,
Yu/Choi/Zhang does not explicitly disclose that the binding reinforcement layer comprises silicon oxynitride (SiON).
In an analogous art, Dias discloses that the binding reinforcement layer comprises silicon oxynitride (SiON) (Para 0013 – underfill material can comprise of silicon oxynitride). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu/Choi/Zhang’s device by having Dia’s disclosure in order to protect different components of a semiconductor device during processing.
Claims 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yu/Choi/Zhang in view of KR (KR 102523694, hereinafter KR).
With respect to claim 20, Yu/Choi/Zhang discloses the semiconductor package of claim 18.
Yu/Choi/Zhang does not explicitly disclose wherein a thickness of the binding reinforcement layer is 100 nm to 3 µm.
In an analogous art, KR discloses wherein a thickness of the binding reinforcement layer is 100 nm to 3 µm (page 12, para 01; page 13; para 01 – thickness 200 nm). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yu/Choi/Zhang’s device by having KR’s disclosure in order to achieve the optimal performance of the semiconductor device.
Allowable Subject Matter
Claims 7-8 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 7, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the binding reinforcement layer is on an upper surface, side surfaces, and a lower surface of the semiconductor chip, the binding reinforcement layer surrounding the plurality of chip connection members, and wherein the encapsulation member fills a space between the semiconductor chip and the first wiring structure” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 16, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the binding reinforcement layer is on the upper surface of the first rewiring insulating layer, a portion of side surfaces of the plurality of first upper surface connection pads protruding from the upper surface of the first rewiring insulating layer, a portion of the upper surface of the plurality of first upper surface connection pads, the portion of the upper surface not being in contact with the plurality of connection structures, and side surfaces of the plurality of connection structures” when considered as a whole along with other claimed limitations.
Claims 8 and 17 are objected because of their dependency on claim 7 & 16 respectively.
Conclusion
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/MOHAMMAD M CHOUDHRY/ Primary Examiner, Art Unit 2899
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