DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 in the reply filed on 2/2/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) s 1-2, 6-10 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lee et al (US 2022/0085011).
1. An integrated circuit device, comprising:
a substrate (Fig.s 1-4 (110) and [0024-0027]);
a fin-type active region (Fig.s 1-4 (FA) and [0029]) on the substrate (Fig.s 1-4 (110) and [0024-0027]), the fin-type active region extending in a first direction (Fig.s 1-4 (FA) and [0029]);
a plurality of semiconductor patterns (Fig.1-4 (SD) and [0049-0054]) spaced apart from an upper surface of the fin- type active region (Fig.s 1-4 (FA) and [0029]) and comprising a channel region [0050- fin is the channel];
a gate electrode (Fig.s 1-4 (124) and [0033]) extending in a second direction [0031] on the fin-type active region (Fig.s 1-4 (FA) and [0029]), disposed between the plurality of semiconductor patterns (Fig.1-4 (SD) and [0049-0054]), and comprising a first sidewall (Fig.s 1-4 (124) and [0044]) extending in the second direction and a second sidewall (Fig.s 1-4 (126) and [0032/0035]) extending in the first direction, the second direction intersecting with the first direction (the x and y directions intersect); and
a gate cut insulating pattern (Fig.4/6/11 (132/134/ CR1A/CR2B) and [0039-0041/0062-0065]) on the second sidewall of the gate electrode (Fig. 4/6/11 (GLA/GLB- 124 ) and [0039/0062]),
wherein an upper portion of the gate cut insulating pattern (Fig.12 (132/CR2B) and [0039-0041/0062]) has a first width (Fig.6/11 (w11) and [0046/0064-0065]) in the second direction, wherein a lower portion of the gate cut insulating pattern (Fig.12 (134/CR1A) and [0039-0041/0062]) has a second width (Fig.6/11 (w12) and [0046/0064-0065]) in the second direction, wherein the second width is smaller than the first width [0064-0065], and wherein a portion of a sidewall of the gate cut insulating pattern is curved (Fig.12 (CRT) and [0082]).
2. The integrated circuit device of claim 1, wherein the second sidewall of the gate electrode (Fig. 6/11 (GLA/GLB- 124 ) and [0062]) comprises a shoulder portion corresponding to the portion of the sidewall of the gate cut insulating pattern (Fig.6/11 (CR1A/132 and CR2B/134 and GLR1) and [0062-0065]).
6. The integrated circuit device of claim 1, further comprising: a gate insulating layer (Fig.3-4 (122) and [0032]) surrounding the first sidewall of the gate electrode (Fig.3 (124) and [0032]), the second sidewall of the gate electrode (Fig.3 (122/124) and [0032]), and a bottom surface of the gate electrode (Fig.3 (122/124) and [0032]), wherein the gate insulating layer (Fig.4 (122) and [0032]) is conformally disposed on a lower sidewall of the gate cut insulating pattern (Fig.4 134) and [0044]) and an upper sidewall of the gate cut insulating pattern (Fig.4 (132) and [0044]).
7. The integrated circuit device of claim 6, wherein: the gate insulating layer (Fig.3-4 (122) and [0032]) is disposed between the gate electrode (Fig.3 (124) and [0032]) and the gate cut insulating pattern (Fig.4 (132/134) and [0044]), and the gate electrode (Fig.3 (124) and [0032]) is spaced apart from the gate cut insulating pattern (Fig.4 (132/134) and [0044]).
8. The integrated circuit device of claim 1, further comprising: an inter-gate insulating layer disposed on the substrate (Fig.3 (126/128) and [0035-0037]), on the first sidewall of the gate electrode, and on a sidewall of the gate cut insulating pattern (Fig.3 (126/128) and [0035-0037]).
9. The integrated circuit device of claim 1, further comprising: a device isolation layer (Fig. 4 (114) and [0029]) disposed on the substrate (Fig. 4 (110) and [0024-0027]) and a sidewall of the fin-type active region (Fig.4 (FA) and [0029]), wherein a bottom surface of the gate cut insulating pattern (Fig.4 (132/134) and [0039-0041]) is disposed on an upper surface of the device isolation layer (Fig. 4 (114) and [0029]).
10. The integrated circuit device of claim 1, further comprising: a device isolation layer (Fig. 4 (114) and [0029]) disposed on the substrate (Fig. 4 (110) and [0024-0027]) and a sidewall of the fin-type active region (Fig.4 (FA) and [0029]); and a bottom insulating pattern (Fig.4 (112) and [0029]) between the device isolation layer (Fig. 4 (114) and [0029]) and a bottom surface of the gate cut insulating pattern (Fig.4 (132/134) and [0039-0041]), wherein a third width in the second direction of the bottom insulating pattern (Fig.4 (112) and [0029]) is smaller than the second width in the second direction of the lower portion of the gate cut insulating pattern (Fig.4 (132/134) and [0039-0041]).
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art teaches the limitations of claims 1-2 as cited above, however fails to teach nor suggest the combination of claims 1+2+3 as required by the dependency of claim 3 and is recited as follows:
3. The integrated circuit device of claim 2, wherein: an uppermost semiconductor pattern among the plurality of semiconductor patterns comprises a first side surface facing the gate cut insulating pattern, and a first distance in a vertical direction between an upper surface of the uppermost semiconductor pattern and the shoulder portion of the second sidewall of the gate electrode is greater than or equal to approximately 80% and is smaller than or equal to approximately 120% of a second distance in the second direction between the first side surface of the uppermost semiconductor pattern and the shoulder portion of the second sidewall of the gate electrode.
Claims 4-5 depend from claim 3 (and claims 1-2) and therefore also contain the combination of allowable subject matter and are recited below:
4. The integrated circuit device of claim 3, wherein a third distance in the vertical direction between the upper surface of the uppermost semiconductor pattern and an upper surface of the gate electrode is greater than the first distance.
5. The integrated circuit device of claim 3, wherein: the second distance is greater than or equal to approximately 5 nanometers (nm); and the second distance is less than or equal to approximately 15 nm.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al (US 12288788); Jung et al (US 2022/0344463) and Park et al (US2022/0399452) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
4/2/26
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