Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-4, 6 and 8 are rejected under 35 U.S.C. 102(a1) as being anticipated by Balakrishnan et al. (US 9,653,289; hereinafter Balakrishnan).
Regarding claim 1, Balakrishnan, in figs. 18-19, discloses a gate-all-around field effect transistor comprising: a plurality of channels 140 formed on a substrate 110/120 to be spaced apart from each other and each comprising a first side surface (left side) and a second side surface (right side) at opposite sides in one direction; a plurality of gate stacks 230/250 each having a gate-all-around (GAA) structure surrounding at least a portion of the channel 140 and comprising a first side surface (left side) and a second side surface (right side) at the opposite sides in the one direction; a source/drain 200 disposed at one side of the gate stacks 230/250 and contacting the plurality of channels 140; and a first internal spacer 180 and a second internal spacer 180 disposed between one side surface of at least one gate stack 230/250 among the plurality of gate stacks 230/250 and the source 200 and between the other side surface of the at least one gate stack 230/250 and the drain 200, respectively, wherein, in the one direction, a distance from one side surface of at least one channel 140 among the plurality of channels 140 to the other side surface thereof is shorter than a distance from one side surface of the first internal spacer 180 adjoining the source 200 to one side surface of the second internal spacer 180 adjoining the drain 200.
Regarding claim 2, Balakrishnan discloses wherein, in the one direction, a first end of a source region 200 or a drain region 200 adjacent the one side surface of the channel 140 extends beyond a second end of the source region 200 or the drain region 200 adjoining the first and second internal spacers 180 (fig. 19).
Regarding claim 3, Balakrishnan discloses wherein the first end of the source 200 or the drain 200 extends beyond the second end in one direction by a length less than a thickness of the first or second internal spacer 180 (fig. 19).
Regarding claim 4, Balakrishnan discloses wherein the first end of the source or the drain 200 extends beyond the second end in one direction by a length greater than 0% to less than 100% of a thickness of the first or second internal spacer 180 (fig. 19).
Regarding claim 6, Balakrishnan discloses wherein a distance from one side surface of the channel 140 to the other side surface of the channels 140 is shorter than a distance from a first side surface of the first internal spacer 180 disposed between the gate stack 230/250 on the channel 140 and the source 200 or the drain 200 to a second side surface of the second internal spacer 180 disposed between the gate stack 230/250 and the source 200 or the drain 200 (fig. 19).
Regarding claim 8, Balakrishnan discloses further comprising: a buried oxide layer inside the substrate or between the substrate and the source/drain (col. 5, lines 13-19).
2. Claims 1-6 and 8 are rejected under 35 U.S.C. 102(a1) as being anticipated by Miao et al. (US 2020/0052124; hereinafter Miao).
Regarding claim 1, Miao, in fig. 12, discloses a gate-all-around field effect transistor comprising: a plurality of channels 14C formed on a substrate 10 to be spaced apart from each other and each comprising a first side surface (left side) and a second side surface (right side) at opposite sides in one direction; a plurality of gate stacks 36/38 each having a gate-all-around (GAA) structure surrounding at least a portion of the channel 14C and comprising a first side surface (left side) and a second side surface (right side) at the opposite sides in the one direction; a source/drain 32 disposed at one side of the gate stacks 36/38 and contacting the plurality of channels 14C; and a first internal spacer 24 and a second internal spacer 24 disposed between one side surface of at least one gate stack 36/38 among the plurality of gate stacks 36/38 and the source 32 and between the other side surface of the at least one gate stack 36/38 and the drain 32, respectively, wherein, in the one direction, a distance from one side surface of at least one channel 14C among the plurality of channels 14C to the other side surface thereof is shorter than a distance from one side surface of the first internal spacer 24 adjoining the source 32 to one side surface of the second internal spacer 24 adjoining the drain 32.
Regarding claim 2, Miao discloses wherein, in the one direction, a first end of a source region 32 or a drain region 32 adjacent the one side surface of the channel 14C extends beyond a second end of the source region 32 or the drain region 32 adjoining the first and second internal spacers 24 (fig. 12).
Regarding claim 3, Miao discloses wherein the first end of the source 32 or the drain 32 extends beyond the second end in one direction by a length less than a thickness of the first or second internal spacer 24 (fig. 12).
Regarding claim 4, Miao discloses wherein the first end of the source or the drain 32 extends beyond the second end in one direction by a length greater than 0% to less than 100% of a thickness of the first or second internal spacer 24 (fig. 12).
Regarding claim 5, Miao discloses wherein a distance from one side surface of the channel 14C to the other side surface of the channel 14C is greater than a width of the gate stack 36/38 placed on the channel 14C (fig. 12).
Regarding claim 6, Miao discloses wherein a distance from one side surface of the channel 14C to the other side surface of the channels 14C is shorter than a distance from a first side surface of the first internal spacer 24 disposed between the gate stack 36/38 on the channel 14C and the source 32 or the drain 32 to a second side surface of the second internal spacer 24 disposed between the gate stack 36/38 and the source 32 or the drain 32 (fig. 12).
Regarding claim 8, Miao discloses further comprising: a buried oxide layer inside the substrate or between the substrate and the source/drain ([0026]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Balakrishnan (US 9,653,289) in view of Frougier et al. (US 9,991,352; hereinafter Frougier).
Balakrishnan discloses a semiconductor device as above but fails to disclose a punch-through-stopper (PTS) region.
However, Frougier discloses a PTS region on the substrate (col. 6, lines 35-38). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form PTS region as taught by Frougier in order to reduce the undesirable flow of charge carriers.
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818