DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 12-16 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2004/0196724 A1), and further in view of Chhabra et al. (US 2022/0199629 A1).
Regarding claim 12, Chen teaches a device comprising:
a power-gate structure configured to selectively cut-off power to power-gated circuitry, the power-gate structure having a header transistor and a footer transistor (Fig. 3, the power-gate structure comprises the header transistor 312 and footer transistor 322. The power-gate structure selectively cut-off power to the power-gated circuitry 330),
wherein the header transistor is coupled between a positive voltage supply and a first intermediate voltage supply based on the positive voltage supply (header transistor 312 is coupled between a positive voltage supply VDD and a first intermediate voltage supply Vload),
wherein the footer transistor is coupled between a ground voltage supply and a second intermediate voltage supply based on the ground voltage supply (footer transistor 322 is coupled between the ground voltage supply GND and the second intermediate voltage supply Virtual GND),
the header transistor comprises a P-type transistor (header transistor 312 is P-type transistor),
the footer transistor comprises an N-type transistor (Footer transistor 322 is N-type transistor), and
Chen is silent in teaching header transistor and the footer transistor are formed with a complementary field effect transistor (CFET) technology such that the P-type transistor is physically disposed on the N-type transistor in a P-over-N (PN) configuration or such that the N-type transistor is physically disposed on the P-type transistor in an N-over-P (NP) configuration.
Chhabra teaches the first transistor and the second transistor are formed with a complementary field effect transistor (CFET) technology such that the P-type transistor is physically disposed on the N-type transistor in a P-over-N (PN) configuration or such that the N-type transistor is physically disposed on the P-type transistor in an N-over-P (NP) configuration (The semiconductor is fabricated using complimentary FET (CFET), ¶0011).
It would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to use complementary field effect transistor (CFET) technology such that the P-type transistor is physically disposed on the N-type transistor in a P-over-N (PN) configuration or such that the N-type transistor is physically disposed on the P-type transistor in an N-over-P (NP) configuration in order to reduce the size of the area used for the fabrication which will help increase the density for the memory device.
Regarding claim 13, Chhabra further teaches the device of claim 12, wherein the first transistor and the second transistor have a split-gate configuration such that a gate of the first transistor is coupled to a header control signal and such that a gate of the second transistor is coupled to a footer control signal that is different than the header control signal (Fig. 2A, the gate for T2 and T3 can be split gate configuration. In additional, when T5 is ON, the ground voltage, which is the third voltage node, will be provided to the gate for T2 and T3. The ground voltage can be considered a control signal).
Regarding claim 14, Chen teaches the device of claim 12, wherein: a header control signal is coupled to a gate of the header transistor, and the header transistor operates to power-gate a circuit by way of the header control signal that is used to activate and deactivate the header transistor (
P
D
controls the header transistor 312 to activate and deactivate the header transistor)
Regarding claim 15, Chen teaches the device of claim 12, wherein: a footer control signal is coupled to a gate of the footer transistor, and the footer transistor operates to power-gate a circuit by way of the footer control signal that is used to activate and deactivate the footer transistor (Pd controls the footer transistor 322 to activate and deactivate the footer transistor).
Regarding claim 16, Chen teaches the device of claim 12, wherein: a header control signal is coupled to a gate of the header transistor, and the header transistor operates to power-gate a first circuit by way of the header control signal that is used to activate and deactivate the header transistor (
P
D
controls the header transistor 312 to activate and deactivate the header transistor to operate the power-gate circuit 354), wherein: a footer control signal is coupled to a gate of the footer transistor, and the footer transistor operates to power-gate a second circuit by way of the footer control signal that is used to activate and deactivate the footer transistor, and the second circuit is different from the first circuit (Pd controls the footer transistor 322 to activate and deactivate the footer transistor to operate the power-gate circuit 352, which is different than the first circuit 354).
Regarding claim 22, Chen teaches the device of claim 12, wherein the power-gate structure is configured to selectively provide or cut-off the first intermediate voltage supply or the second intermediate voltage supply to the power-gated circuitry (Fig. 3, transistors 312 and 322 selectively provide or cut-off the first intermediate voltage supply or the second intermediate voltage supply to the power-gated circuitry).
Allowable Subject Matter
Claims 1, 2, 4, 6-11, 18-21 and 23 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
After further search and consideration it is determined that the prior art of record neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach, the following limitation(s) in combination with the remaining claimed limitation:
With regards to claim 1, a power-gate structure configured to selectively cut-off power to power-gated circuitry, the power-gate structure having multiple transistors including a first transistor and a second transistor, wherein the first transistor is coupled between a first voltage node and a second voltage node, wherein the second transistor is coupled between the second voltage node and a third voltage node that is directly coupled to the second voltage node, wherein the first transistor comprises a P-type transistor, wherein the second transistor comprises an N-type transistor.
With regards to claim 18, coupling a first transistor of a power-gate structure between a first voltage node and a second voltage node, wherein the power-gate structure is configured to selectively cut-off power to power-gated circuitry: coupling a second transistor of the power-gate structure between the second voltage node and a third voltage node; directly coupling the second voltage node to the third voltage node, wherein the first transistor comprises a P-type transistor, wherein the second transistor comprises an N-type transistor.
Response to Arguments
Applicant's arguments filed 06/02/2026 have been fully considered but they are not persuasive.
Applicant’s representative argues on bottom of page 9 “Chhabra pertains to a memory cell structure rather than to a power-gate structure. The only disclosure in Chhabra about PN or NP structures pertains to memory cells; not to a power-gate structure. Thus, Chen in view of Chhabra would, at most, only disclose that Chen's memory cells 342 could be implemented with PN or NP structures. Chen in view of Chhabra does not disclose that Chen's disparate head switch 310 and foot switch 320 coupled to different nodes are PN or NP structures.” And on top of page 10 “Chen in view of Chhabra does not disclose the claimed header and footer transistors in a power-gate structure implemented in a PN or NP structure. Chen in view of Chhabra also does not disclose any motivation to modify Chen's high Vt PMOS 312 and high Vt NMOS 322 into a PN or NP structure. Chen's high Vt PMOS 312 and high Vt NMOS 322 are in different locations coupled to different nodes. Furthermore, Chen's high Vt PMOS 312 and high Vt NMOS 322 are significantly larger and serve different purposes than the low Vt, high-speed, bitcell transistors in Chhabra. The disclosure the Office Action has asserted underlying the rejection is simply not disclosed by either reference alone or together.”
Chen teaches header and footer transistors which are used to control the power supplied to the memory device. Header and Footer transistors are common in the memory area which are used to turn OFF peripheral circuitries or memory arrays when are not in use to reduce energy use. Most of these transistors are formed using planar FETs transistors and FinFETs transistors. Lately, new technologies have emerged such as GAAFETS and CFETS to make transistors in the memory device. Currently, claim 1 is using a new technology to make the header and footer transistors. Just using the new technology to make the header and footer transistors is obvious to any person with the ordinary skills in the art. CFETs represent a type of transistor design that includes both n-type and p-type transistors forming a complementary pairs. In this case, the header and footer transistors taught by Chen are formed using n-type and p-type transistors, which are complementary transistors and CFET manufacturing will be ideal.
Applicant’s representative argues on page 10 “ Furthermore, Chhabra is not analogous art because Chhabra (i) does not have "essentially the same function and structure" as and (ii) logically would [NOT] have commended itself to one of ordinary skill concerned with "mitigat[ing] dynamic IR drop on power grids in modern circuitry by providing more effective power-gate schemes for circuit based applications."”
Chen teaches the CMOS integrated circuit is an SRAM type memory device. Also, Chhabra teaches the memory device to be an SRAM type memory device. Both reference are analogous art and are in the same field.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824
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