DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tung (US 2019/0252366).
Regarding claim 1, Tung discloses a semiconductor structure, comprising:
a base, comprising a substrate (100, figs. 1-3 and paragraph 0023) and a plurality of fins (101, 102, 103, 104, figs. 1-4 and paragraph 0023) arranged in parallel on the substrate, the substrate comprising a transistor cell area for forming transistors (fig. 7 and paragraphs 0036-0039 teaches multiple transistor regions 301, 302, 303, 304, 305, 306), and in the transistor cell area, in a direction perpendicular to an extending direction of the fins of the plurality of fins, a fin of the plurality of fins closest to a boundary of the transistor cell area is used as an edge fin (101, figs. 1-3, 7 and paragraphs 0026, 0031), and the edge fin having an outer side wall facing the boundary of the transistor cell area (fin 101 edge of 101b, figs. 1-3, 7); and
a gate structure (333, 363, fig. 3 and paragraph 0030), located on the base and spanning the fins of the plurality of fins, the gate structure covering a part of a top and a part of a side wall of the fins of the plurality of fins, and the gate structure exposing an entire outer side wall of the edge fin (101b, fig. 3 and paragraphs 0023-0031).
Regarding claim 2, Tung further discloses wherein:
the gate structure exposes the entire outer side wall of the edge fin and also
exposes a part of a top of the edge fin (101, fig. 3 and paragraph 0031); or
the gate structure exposes the entire outer side wall of the edge fin and also
exposes the top of the edge fin (101, fig. 5 and paragraph 0032).
Regarding claim 3, Tung further discloses wherein:
the substrate comprises a plurality of transistor cell areas (fig. 7 and paragraphs 0036-0039 teaches multiple transistor regions 301, 302, 303, 304, 305, 306);
in each transistor cell area of the plurality of transistor cell areas, a fin of the
plurality of fins closest to a junction of adjacent transistor cell areas of the plurality of
transistor cell areas is used as the edge fin (fig. 7); and
portions of the gate structure in the adjacent transistor cell areas of the plurality of transistor cell areas are isolated (fig. 7 and paragraphs 0036-0039).
Regarding claim 4, Tung further discloses wherein:
the base further comprises: an isolation layer, located on a portion of the
substrate exposed by fins of the plurality of fins, the isolation layer covering a part of the
side wall of fins of the plurality of fins (110, figs. 1-3 and paragraph 0023); and
in the transistor cell areas of the plurality of transistor cell areas, in a direction
perpendicular to the extending direction of the plurality of fins, the edge fin
corresponding to an outer side wall exposed by the gate structure has a first bottom
width on a top surface of the isolation layer, and the remaining fins of the plurality of fins have a second bottom width on the top surface of the isolation layer, the first bottom width being less than the second bottom width (fig. 3).
Regarding claim 5, Tung further discloses wherein the gate structure is a device gate structure, and the device gate structure comprises a metal gate (333, paragraph 0030).
Regarding claim 6, Tung further discloses wherein the gate structure is a device gate structure, and the device gate structure comprises a gate dielectric layer and a gate layer covering the gate dielectric layer (fig. 3 and paragraph 0030).
Regarding claim 7, Tung further discloses wherein the semiconductor structure further comprises a gate oxide layer, the gate oxide layer being located between the gate structure and a fin of the plurality of fins, or the gate oxide layer located between the gate structure and a fin of the plurality of finds and also extending to cover an outer side wall exposed by the gate structure (paragraphs 0025-0027).
Regarding claim 8, Tung further discloses wherein a material of the gate oxide layer comprises at least one of silicon oxide or silicon oxynitride (paragraph 0025).
Regarding claim 9, Tung further discloses wherein in a direction perpendicular to the extending direction of the fins of the plurality of fins, a top width of the fins of the plurality of fins is greater than a bottom width of the fins of the plurality of fins (paragraphs 0023-0024).
Regarding claim 11, Tung further discloses wherein a material of the gate layer comprises at least one of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN or TiAIC (paragraph 0027).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Tung (US 2019/0252366).
Regarding claim 10, Tung further discloses wherein a material of the gate dielectric layer comprises a high-k dielectric layer (paragraph 0027). Tung does not explicitly list HfO₂, ZrO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3 as the high-k dielectric layer. However, the Examiner takes official notice that such materials are the most common high-k dielectrics used for gate insulators.
Response to Arguments
Applicant’s arguments with respect to the amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/ Primary Examiner, Art Unit 2897 3/29/26
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