DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed August 8, 2025 have been entered and considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 6168984 B1), in view of Cheng et al. (US 20110108930 A1), Chang et al. (US 10957777 B2), Hu (US 20080135903 A1), and Cho et al. (US 7074661 B2).
Regarding claim 1, Yoo et al. (region 99) teaches:
A semiconductor device, comprising:
a substrate [1/70, Col. 4, Lines 51-65, Fig. 1-10];
a first gate structure [14 (Left), Col. 6, Lines 65-67 to Col. 7, Lines 1-5, Fig. 6-10] positioned on the substrate [1/70], comprising:
a first gate insulating layer [9, Col. 6, Lines 47-51, Fig. 6-10] positioned on the substrate [1/70];
a first gate conductive layer [11, Col. 6, Lines 57-67 to Col. 7, Lines 1-5, Fig. 6-10] positioned on the first gate insulating layer [9]; and
a first gate capping layer [13, Col. 6, Lines 60-67 to Col 7, Lines 1-5, Fig. 6-10] positioned on the first gate conductive layer [11];
a second gate structure [14 (Right)] positioned on the substrate [1/70] and next to the first gate structure [14 (Left)];
an impurity region [15, 15, Col. 7, Lines 6-16, Fig. 7-10] positioned in the substrate [1/70, Fig. 1-10] and between the first gate structure [14(left), Fig. 7-10] and the second gate structure [14(right), Fig. 7-10];
a dielectric layer [17, Col. 7, Lines 24-31, Fig. 8-10] positioned on the substrate [1/70] and covering the first gate structure [14 (Left)] and the second gate structure [14 (Right)]; and
a first opening [21b, Col. 7, Lines 51-61, Fig. 9-10] positioned along the dielectric layer [17] to expose a top surface of the first gate capping layer [13, Col. 7, Lines 51-61, Fig. 9-10], such that the exposed top surface of the first gate capping layer [13, Fig. 9-10] form a bottom wall of the first opening [21b, Fig. 9-10];
wherein the first gate capping layer [13, Col. 6, Lines 62-65, Fig. 6-10] comprises silicon nitride, silicon oxynitride, or silicon nitride oxide;
wherein a top surface of the first gate structure [14 (Left)], a top surface of the second gate structure [14 (Right)] are substantially coplanar.
Yoo et al. teaches in the same embodiment but in a different region (88):
an assistance layer [8, in region 88, Col. 6, Lines, 29-35, Fig. 5-10] positioned on the impurity region [7a/7b, Col. 6, Lines 7-12, Fig. 4-10];
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yoo et al. (region 88) into the teachings of Yoo et al. (region 99) to include an assistance layer positioned on the impurity region. The ordinary artisan would have been motivated to modify Yoo et al. in the above manner for the purpose of reducing resistance and improving performance.
Yoo et al. (region 88 and 99) discloses the above claimed subject matter.
However, Yoo et al. (region 88 and 99) does not teach:
a layer of energy-removable material positioned on the assistance layer and between the first gate structure and the second gate structure.
wherein a bottom surface of the assistance layer is lower than a top surface of the impurity region.
Cheng et al. teaches:
a layer of energy-removable material [ILD 24, paragraph [0028-0029], Fig. 1-4] positioned on the assistance layer [22 (SIL), paragraph [0028-0029], Fig. 1-4] and between the first gate structure [Gate 18 (left), paragraph [0028], Fig. 1-4] and the second gate structure [Gate 18 (right), paragraph [0028], Fig. 1-4].
wherein a bottom surface of the assistance layer [22 (SIL), paragraph [0028-0029], Fig. 1-4] is lower than a top surface of the impurity region [16 (S/D), paragraph [0028], Fig. 1-4].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Cheng et al. into the teachings of Yoo et al. (region 88 and 99) to include a layer of energy-removable material positioned on the assistance layer and between the first gate structure and the second gate structure, wherein a bottom surface of the assistance layer is lower than a top surface of the impurity region. The ordinary artisan would have been motivated to modify Yoo et al. (region 88 and 99) in the above manner for the purpose of reducing resistance and improving performance.
Yoo et al. (region 88 and 99), and Cheng et al. disclose the above claimed subject matter.
However, Yoo et al. (region 88 and 99), and Cheng et al. do not teach:
a first opening positioned along the dielectric layer to expose a top surface of the layer of energy-removable material, such that the top surface of the layer of energy-removable material form a bottom wall of the first opening.
wherein a top surface of the first gate structure, a top surface of the second gate structure, and the top surface of the layer of energy-removable material are substantially coplanar.
Chang et al. teaches:
a first opening [181, Col. 7, Lines 61-64, Fig. 7] positioned along the dielectric layer [180, Col. 7, Lines 61-64, Fig. 7] to expose a top surface of the layer of energy-removable material [171, Col. 7, Lines 61-64, Fig. 7], such that the top surface of the layer of energy-removable material [171, Col. 7, Lines 61-64, Fig. 7] form a bottom wall of the first opening [181].
wherein a top surface of the first gate structure [121, Col. 5, Lines 15-17, Fig. 8], a top surface of the second gate structure [123, Col. 5, Lines 15-17, Fig. 8], and the top surface of the layer of energy-removable material [171, Fig. 5-8] are substantially coplanar [Fig. 5-8].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chang et al. into the teachings of Yoo et al. (region 88 and 99), and Cheng et al. to include a first opening positioned along the dielectric layer to expose a top surface of the layer of energy-removable material, such that the top surface of the layer of energy-removable material form a bottom wall of the first opening. Wherein a top surface of the first gate structure, a top surface of the second gate structure, and the top surface of the layer of energy-removable material are substantially coplanar. The ordinary artisan would have been motivated to modify Yoo et al. (region 88 and 99), and Cheng et al. in the above manner for the purpose of increasing density, connection surfaces and performance of device. Also, a coplanar surface increases the density and symmetry within the device, reducing resistance and improving performance.
Yoo et al. (region 88 and 99), Cheng et al., and Chang et al. disclose the above claimed subject matter.
However, Yoo et al. (region 88 and 99), Cheng et al., and Chang et al. do not teach:
wherein the first gate insulating layer comprises a high-k material.
Hu teaches:
wherein the first gate insulating layer [18/18o, paragraph [0024], Fig. 12-13] comprises a high-k material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Hu into the teachings of Yoo et al. (region 88 and 99), Cheng et al., and Chang et al. to include wherein the first gate insulating layer comprises a high-k material. The ordinary artisan would have been motivated to modify Yoo et al. (region 88 and 99), Cheng et al., and Chang et al. in the above manner for the purpose of allowing the thickness of the layer to be increased at the same capacitance and suppressing leakage effects. Also, a high-k material will reduce power consumption, increase speed and improve performance.
Yoo et al. (region 88 and 99), Cheng et al., Chang et al., and Hu disclose the above claimed subject matter.
However, Yoo et al. (region 88 and 99), Cheng et al., Chang et al., and Hu do not teach:
wherein the top surface of the layer of energy-removable material is extended between the top surface of the first gate structure and the top surface of the second gate structure.
Cho et al. teaches:
wherein the top surface of the layer of energy-removable material [31, Col. 3, Lines 63-67; Col. 4, Lines 27-31, Fig. 3D] is extended between the top surface of the first gate structure [20 (Left), Col. 3, Lines 45-46, Fig. 3C] and the top surface of the second gate structure [20 (Right)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Cho et al. into the teachings of Yoo et al. (region 88 and 99), Cheng et al., Chang et al., and Hu to include wherein the top surface of the layer of energy-removable material is extended between the top surface of the first gate structure and the top surface of the second gate structure. The ordinary artisan would have been motivated to modify Yoo et al. (region 88 and 99), Cheng et al., Chang et al., and Hu in the above manner for the purpose of completely filling the opening, increasing contact surface and creating better connections, therefore increasing performance.
[MPEP 2141 (I) The KSR Decision and Principles of the Law of Obviousness]
The Supreme Court in KSR reaffirmed the familiar framework for determining obviousness as set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), but stated that the Federal Circuit had erred by applying the teaching-suggestion-motivation (TSM) test in an overly rigid and formalistic way. KSR, 550 U.S. at 404, 82 USPQ2d at 1391. Specifically, the Supreme Court stated that the Federal Circuit had erred in four ways: (1) "by holding that courts and patent examiners should look only to the problem the patentee was trying to solve " (Id. at 420, 82 USPQ2d at 1397); (2) by assuming "that a person of ordinary skill attempting to solve a problem will be led only to those elements of prior art designed to solve the same problem" (Id.); (3) by concluding "that a patent claim cannot be proved obvious merely by showing that the combination of elements was ‘obvious to try’" (Id. at 421, USPQ2d at 1397); and (4) by overemphasizing "the risk of courts and patent examiners falling prey to hindsight bias" and as a result applying "[r]igid preventative rules that deny factfinders recourse to common sense" (Id.). See also Novartis Pharms. Corp. v. West-Ward Pharms. Int'l Ltd., 923 F.3d 1051, 1059, 2019 USPQ2d 171676 (Fed. Cir. 2019); Apple Inc. v. Samsung Elecs. Co., 839 F.3d 1034, 1047-48, 120 USPQ2d 1400, 1410 (Fed. Cir. 2016); and Aventis Pharma S.A. v. Hospira, Inc., 675 F.3d 1324, 1332, 102 USPQ2d 1445, 1449 (Fed. Cir. 2012).
In KSR, the Supreme Court particularly emphasized "the need for caution in granting a patent based on the combination of elements found in the prior art, "Id. at 415, 82 USPQ2d at 1395, and discussed circumstances in which a patent might be determined to be obvious. Importantly, the Supreme Court reaffirmed principles based on its precedent that "[t]he combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. "Id. at 415-16, 82 USPQ2d at 1395. The Supreme Court stated that there are "[t]hree cases decided after Graham [that] illustrate this doctrine." Id. at 416, 82 USPQ2d at 1395. (1) "In United States v. Adams, . . . [t]he Court recognized that when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable result." Id. (2) "In Anderson’s-Black Rock, Inc. v. Pavement Salvage Co., . . . [t]he two [pre-existing elements] in combination did no more than they would in separate, sequential operation." Id. at 416-17, 82 USPQ2d at 1395. (3) "[I]n Sakraida v. AG Pro, Inc., the Court derived . . . the conclusion that when a patent simply arranges old elements with each performing the same function it had been known to perform and yields no more than one would expect from such an arrangement, the combination is obvious." Id. at 417, 82 USPQ2d at 1395-96 (Internal quotations omitted.). The principles underlining these cases are instructive when the question is whether a patent application claiming the combination of elements of prior art would have been obvious. The Supreme Court further stated that:
When a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or a different one. If a person of ordinary skill can implement a predictable variation, § 103 likely bars its patentability. For the same reason, if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill. Id. at 417, 82 USPQ2d at 1396.
When considering obviousness of a combination of known elements, the operative question is thus "whether the improvement is more than the predictable use of prior art elements according to their established functions." Id.
The Supreme Court’s flexible approach to the obviousness inquiry is reflected in numerous pre-KSR decisions; see MPEP § 2144. That section provides many lines of reasoning to support a determination of obviousness based upon earlier legal precedent that had condoned the use of particular examples of what may be considered common sense or ordinary routine practice (e.g., making integral, changes in shape, making adjustable). Thus, the type of reasoning sanctioned by the opinion in KSR has long been part of the patent examination process.
[MPEP 2141 (II)(C) Resolving the Level of Ordinary Skill in the Art]
"A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton. "KSR, 550 U.S. at 421, 82 USPQ2d at 1397. "[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle. "Id. at 420, 82 USPQ2d at 1397. Office personnel may also take into account "the inferences and creative steps that a person of ordinary skill in the art would employ. "Id. at 418, 82 USPQ2d at 1396.”
Regarding claim 2, Yoo et al. (region 88 and 99), Cheng et al., Chang et al., Hu and Cho et al. teach the semiconductor device of claim 1.
Yoo et al. (region 99) further teaches:
further comprising a plurality of first spacers [16, Col. 7, Lines 21-23, Fig. 7-10] positioned between the first gate structure [14 (Left)], and between the second gate structure [14 (Right)]. Wherein a top end of each of the first spacers [16] is coplanar with the top surface of the first gate structure [14 (Left)], and the top surface of the second gate structure [14 (Right)].
Yoo et al. (region 88 and 99), Cheng et al., Chang et al., Hu and Cho et al. disclose the above claimed subject matter.
However, Yoo et al. (region 88 and 99), Cheng et al., Chang et al., and Hu do not teach:
a plurality of first spacers positioned between the first gate structure and the layer of energy-removable material, and between the second gate structure and the layer of energy-removable material, wherein a top end of each of the first spacers is coplanar with the top surface of the first gate structure, the top surface of the second gate structure, and the top surface of the layer of energy-removable material.
Cho et al. teaches:
further comprising a plurality of first spacers [29, Col. 3, Lines 45-48, Fig. 3C-3G] positioned between the first gate structure [20 (Left), Fig. 3C] and the layer of energy- removable material [31, Col. 3, Lines 63-67, Fig. 3D] and between the second gate structure [20 (Right), Fig. 3C] and the layer of energy-removable material [31, Col. 3, Lines 63-67, Fig. 3D], wherein a top end of each of the first spacers [29] is coplanar with the top surface of the first gate structure [20 (Left)], the top surface of the second gate structure [20 (Right)], and the top surface of the layer of energy-removable material [31, Col. 3, Lines 63-67, Fig. 3D].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Cho et al. into the teachings of Yoo et al. (region 88 and 99), Cheng et al., Chang et al., and Hu to include a plurality of first spacers positioned between the first gate structure and the layer of energy-removable material, and between the second gate structure and the layer of energy-removable material, wherein a top end of each of the first spacers is coplanar with the top surface of the first gate structure, the top surface of the second gate structure, and the top surface of the layer of energy-removable material. The ordinary artisan would have been motivated to modify Yoo et al. (region 88 and 99), Cheng et al., Chang et al., and Hu in the above manner for the purpose of increasing density and symmetry within the device, reducing resistance and improving performance.
Regarding claim 3, Yoo et al. (region 88 and 99), Cheng et al., Chang et al., Hu and Cho et al. teach the semiconductor device of claim 2.
Yoo et al. (region 99) further teaches:
further comprising an impurity region [15, Col. 7, Lines 6-16, Fig. 7-10] positioned in the substrate [1/70] and below the first gate structure [14 (Left)] and the second gate structure [14 (Right)], wherein the impurity region [15] is formed between the first gate structure [14 (Left)] and the second gate structure [14 (Right)] in a contactless manner.
Regarding claim 4, Yoo et al. (region 88 and 99), Cheng et al., Chang et al., Hu and Cho et al. teach the semiconductor device of claim 1.
Yoo et al. (region 88 and 99), Cheng et al., Chang et al., Hu and Cho et al. teach the above claimed subject matter.
However, Yoo et al. (region 88 and 99), Cheng et al., Hu and Cho et al. do not teach:
wherein a width of the first opening is greater than a width of the layer of energy-removable material and is greater than a distance between the first gate structure and the second gate structure.
Chang et al. teaches:
wherein a width [See Fig. 7] of the first opening [181] is greater than a width of the layer of energy-removable material [171] and is greater than a distance between the first gate structure [121] and the second gate structure [123].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chang et al. into the teachings of Yoo et al. (region 88 and 99), Cheng et al., Hu and Cho et al. to include wherein a width of the first opening is greater than a width of the layer of energy-removable material and is greater than a distance between the first gate structure and the second gate structure. The ordinary artisan would have been motivated to modify Yoo et al. (region 88 and 99), Cheng et al., Hu and Cho et al. in the above manner for the purpose of creating better connections, preventing short circuits and allowing the upper contact structure to overlap and connect with features, increasing performance.
Regarding claim 5, Yoo et al. (region 88 and 99), Cheng et al., Chang et al., Hu and Cho et al. teach the semiconductor device of claim 1.
Yoo et al. (region 99) further teaches:
wherein two inner surfaces of the dielectric layer [17, Fig. 9] forms two sidewalls of the first opening [21b (top), Col. 7, Lines 51-67 to Col. 7, Lines 1-4, Fig. 9] respectively, wherein the first opening [21b (top), Fig. 9] has a width which is uniform from top to bottom.
Yoo et al. (region 88 and 99), Cheng et al., Chang et al., Hu and Cho et al. disclose the above claimed subject matter.
However, Yoo et al. (region 88 and 99), Cheng et al., Chang et al., and Cho et al. do not teach:
wherein the layer of energy-removable material is configured being removed by an energy source.
Hu further teaches:
wherein the layer of energy-removable material [100, Col. 4, Lines 21-39; Col. 6, Lines 1-5, Fig. 15-25] is configured being removed by an energy source.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Hu into the teachings of Yoo et al. (region 88 and 99), Cheng et al., Chang et al., and Cho et al. to include wherein the layer of energy-removable material is configured being removed by an energy source. The ordinary artisan would have been motivated to modify Yoo et al. (region 88 and 99), Cheng et al., Chang et al., and Cho et al. in the above manner for the purpose of increasing density and symmetry, and preparing for subsequent processes.
Regarding claim 6, Yoo et al. (region 88 and 99), Cheng et al., Chang et al., Hu and Cho et al. teach the semiconductor device of claim 5.
Yoo et al. (region 99) further teaches:
wherein the plurality of first spacers [16, Col. 7, Lines 18-23, Fig. 7-10] comprise silicon nitride, silicon oxynitride, or silicon nitride oxide.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 6168984 B1), in view of Cheng et al. (US 20110108930 A1).
Regarding claim 7, Yoo et al. (region 99) teaches:
A semiconductor device, comprising:
a substrate [1/70, Col. 4, Lines 51-65, Fig. 1-10];
a first gate structure [14 (Left), Col. 6, Lines 65-67 to Col. 7, Lines 1-5, Fig. 6-10] positioned on the substrate [1/70];
a second gate structure [14 (Right), Fig. 6-10] positioned on the substrate [1/70] and next to the first gate structure [14 (Left)];
an impurity region [15, 15, Col. 7, Lines 6-16, Fig. 7-10] positioned in the substrate [1/70, Fig. 1-10] and between the first gate structure [14(left), Fig. 7-10] and the second gate structure [14(right), Fig. 7-10];
a lower portion [See Fig. 10] positioned between the first gate structure [14 (Left)] and the second gate structure [14 (Right)], wherein the lower portion is defined between a top surface of the first gate structure [14 (Left)] and the second gate structure [14 (Right)];
an upper portion [See Fig. 10] positioned on the lower portion above the top surfaces of the first gate structure [14 (Left)] and the second gate structure [14 (Right)]; and
a plurality of first spacers [16, Col. 7, Lines 21-23, Fig. 7-10] positioned between lower portion and the first gate structure [14 (Left)] and between the lower portion and the second gate structure [14 (Right)], wherein a top end of each of the first spacers [16, Fig. 7-10] is coplanar with the top surface of the first gate structure [14 (Left)] and the top surface of the second gate structure [14 (Right)];
wherein the lower portion and the upper portion configure a contact structure [25, Col. 8, Lines 5-19, Fig. 10];
wherein a width of the upper portion is greater than a width of the lower portion [See Fig. 10];
wherein the width of the lower portion is gradually decreased towards the substrate [1/70, Fig. 10];
wherein the first gate structure [14 (Left)] comprises:
a first gate insulating layer [9, Col. 6, Lines 47-51, Fig. 6-10] positioned on the substrate [1/70];
a first gate conductive layer [11, Col. 6, Lines 57-67 to Col. 7, Lines 1-5, Fig. 6-10] positioned on the first gate insulating layer [9]; and
a first gate capping layer [13, Col. 6, Lines 60-67 to Col 7, Lines 1-5, Fig. 6-10] positioned on the first gate conductive layer [11],
wherein the upper portion is in contact with the first gate capping layer [13, Fig. 10].
Yoo et al. teaches in the same embodiment but in a different region (88):
an assistance layer [8, in region 88, Col. 6, Lines, 29-35, Fig. 5-10] positioned on the impurity region [7a/7b, Col. 6, Lines 7-12, Fig. 4-10].
This limitation can be applied to region 99, specifically the limitation “a lower portion positioned between the first gate structure and the second gate structure, wherein the lower portion is defined between a top surface of the assistance layer and top surfaces of the first gate structure and the second gate structure”.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yoo et al. (region 88) into the teachings of Yoo et al. (region 99) to include an assistance layer positioned on the impurity region. The ordinary artisan would have been motivated to modify Yoo et al. in the above manner for the purpose of reducing resistance and improving performance.
Yoo et al. (region 88 and 99) discloses the above claimed subject matter.
However, Yoo et al. (region 88 and 99) does not teach:
wherein a bottom surface of the assistance layer is lower than a top surface of the impurity region, and the assistance layer does not overlap the first spacers from a top view.
Cheng et al. teaches:
wherein a bottom surface of the assistance layer [22 (SIL), paragraph [0028-0029], Fig. 1-4] is lower than a top surface of the impurity region [16 (S/D), paragraph [0028], Fig. 1-4], and the assistance layer [22 (SIL), Fig. 1-4] does not overlap the first spacers [20 (SPA), paragraph [0028], Fig. 1-4] from a top view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Cheng et al. into the teachings of Yoo et al. (region 88 and 99) to include wherein a bottom surface of the assistance layer is lower than a top surface of the impurity region, and the assistance layer does not overlap the first spacers from a top view. The ordinary artisan would have been motivated to modify Yoo et al. (region 88 and 99) in the above manner for the purpose of reducing resistance and improving performance.
Regarding claim 8, Yoo et al. (region 88 and 99), and Cheng et al. teach the semiconductor device of claim 7.
Yoo et al. (region 99) further teaches:
further comprising an impurity region [15, 15, Col. 7, Lines 6-16, Fig. 7-10] positioned in the substrate [1/70] and below the lower portion, and a dielectric layer [17, Col. 7, Lines 24-31, Fig. 8-10] positioned on the substrate [1/70], covering the first gate structure [14 (Left)] and the second gate structure [14 (Right)], and surrounding the upper portion, wherein the first spacers [16] and the lower portion are extended downward to the impurity region [15] of the substrate [1/70, Fig. 10].
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 6168984 B1), in view of Cheng et al. (US 20110108930 A1) as applied to claim 8 above, and further in view of Hu (US 20080135903 A1).
Regarding claim 9, Yoo et al. (region 88 and 99), and Cheng et al. teach the semiconductor device of claim 8.
Yoo et al. (region 99) further teaches:
wherein the plurality of first spacers [16, Col. 7, Lines 18-23, Fig. 7-10] comprise silicon nitride, silicon oxynitride, or silicon nitride oxide.
Yoo et al. (region 88 and 99) and Cheng et al. disclose the above claimed subject matter.
However, Yoo et al. (region 88 and 99), and Cheng et al. do not teach:
wherein the first gate insulating layer comprises a high-k material.
Hu teaches:
wherein the first gate insulating layer [18/18o, paragraph [0024], Fig. 12-13] comprises a high-k material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Hu into the teachings of Yoo et al. (region 88 and 99), and Cheng et al. to include the wherein the first gate insulating layer comprises a high-k material. The ordinary artisan would have been motivated to modify Yoo et al. (region 88 and 99), and Cheng et al. in the above manner for the purpose of allowing the thickness of the layer to be increased at the same capacitance and suppressing leakage effects. Also, a high-k material will reduce power consumption, increase speed and improve performance.
Regarding claim 10, Yoo et al. (region 88 and 99), Cheng et al., and Hu teach the semiconductor device of claim 9.
Yoo et al. (region 99) further teaches:
wherein the first gate capping layer [13, Col. 6, Lines 62-65, Fig. 6-10] comprises silicon nitride, silicon oxynitride, or silicon nitride oxide; wherein the contact structure [25, Col. 8, Lines 5-35, Fig. 10; Col. 11, Lines 40-42, Fig.10] comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, or a combination thereof; wherein the impurity region [15, Col. 7, Lines 6-14, Fig. 7-10] comprises n-type dopants or p-type dopants.
Response to Arguments
Applicant’s arguments with respect to claims 7-8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant argues on pages 1-3, section: Claim Rejections 35 USC §102 (paragraphs [4-9]), in remarks filed August 8, 2025, that primary reference Yoo et al. (US 6168984 B1), does not teach the amendments to independent claim 7. Due to a new line of search and consideration, and in view of Cheng et al. (US 20110108930 A1), the amended limitations of claim 7 can be overcome. Claim 8, which is dependent on independent claim 7, is therefore also rejected for at least the reasons mentioned above.
Applicant’s arguments with respect to claims 1-6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant argues on pages 3-6, section: Claim Rejections 35 USC § 103 (paragraphs [10-20]), in remarks filed August 8, 2025, that current prior art of record does not teach the amendments to independent claim 1. Due to a new line of search and consideration, and in view of Cheng et al. (US 20110108930 A1), the amended limitations of claim 1 can be overcome. Claims 2-6, which are directly or indirectly dependent on independent claim 1, are therefore also rejected for at least the reasons mentioned above.
Applicant’s arguments with respect to claims 7-8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant argues on page 6, section: Claim Rejections 35 USC § 103 (paragraph [21]), in remarks filed August 8, 2025, that current prior art of record does not teach the amendments to independent claim 7, and therefore claims 9-10, which are directly or indirectly dependent on independent claim 7 should also be allowable. Due to a new line of search and consideration, and in view of Cheng et al. (US 20110108930 A1), the amended limitations of claim 7 can be overcome, and therefore all claims directly or indirectly dependent on claim 7 are also rejected for at least the reasons mentioned above.
In summary, after a new line or search and consideration and in view of newly added reference Cheng et al. (US 20110108930 A1), the amendments to independent claims 1 and 7 can be overcome, and all claims directly or indirectly dependent on independent claims 1 and 7 are therefore rejected for at least the reasons mentioned above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.M.H./Examiner, Art Unit 2815 10/23/2025
/MONICA D HARRISON/Primary Examiner, Art Unit 2815