Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US Patent No. 20150179616 A1) in view of Park (US Patent No. 20230014933 A1).
Regarding claim 1, Lin et al. disclose an anti-electromagnetic interference wafer structure in the wafer processing stage (Fig. 2a), comprising: a digital processing unit area with a digital processing unit (430, Fig. 10f, paragraph 126), an insulating layer (178, Fig 3h, paragraph 69), a conducting layer (180), the insulating layer (178) has a top surface on which the conducting layer is coated (180, paragraph 69), and the conducting layer is capable of absorbing electromagnetic interferences passed on to the conducting layer (paragraph 69).
However, Lin et al. do not disclose a plurality of information connectivity points wherein the digital processing unit has a top surface on which the insulating layer and the information connectivity points are designed.
On the other hand, Park discloses the chip pads (124) may include data pads (information connectivity points) (paragraph 33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin et al. according to the teachings of Park such that the digital signal processing (DSP) unit has data pads, or information connectivity points, disposed on the top surface of the digital signal processing unit. Doing so would allow the DSP unit to connect to other devices for input/output of a logic signal or data.
Regarding claim 2, Lin et al. does not mention a grounding connection point for electric conduction between the grounding connection point and the digital processing unit.
However, Park et al. discloses a grounding connection pad (124) for electric conduction between the ground point and digital processing unit (paragraph 33 – pads (124) can be data pads or ground pads).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin et al. according to the teachings of Park et al. such that the grounding connection point is for electric conduction between the connection point and the digital processing unit. Doing so would provide a reference potential of 0V for the circuit and offering a safety path for fault currents.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US Patent No. 20150179616 A1) and Park (US Patent No. 20230014933 A1) as applied to claim 1 above, in further view of Lee et al (US Patent No. 20110304011 A1).
Regarding claim 3, Lin et al teach the digital processing unit area comprises a plurality of via holes (paragraph 91, Fig 6d, 263). Lin et al. does not teach the vias penetrating the conductive layer and the insulating layer.
However, Lee et al. teach the digital processing unit area comprises a plurality of via holes (150), penetrating the conductive layer (148), and the insulating layer (142) (paragraph 49, Fig. 3k).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin et al. according to the teachings of Lee et al. such that the plurality of via holes penetrate the conductive layer and insulating layer according to the claimed invention. Doing so would provide inter-layer connectivity such as vertical routing.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US Patent No. 20150179616 A1), Park (US Patent No. 20230014933 A1), and Lee et al (US Patent No. 20110304011 A1) as applied to claim 3 above, in further view of Iwaki et al. (US Patent No. 10607998 B1).
Regarding claim 5, Lee et al. teach a digital processing unit area comprises a via hole (150) and the conducting layer (148) (paragraph 49).
However, Lin et al. does not teach a plurality of insulating walls, each of which is located at an interface of a via hole and the conducting layer.
On the other hand, Iwaki et al. disclose insulating walls (40) formed on the side conductive vias (36) (paragraph 43, Fig. 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Lee et al. according to the teachings of Iwaki et al. such that the insulating walls are located at an interface of a via hole and the conducting layer. Doing so would avoid interferences created by a conducting layer and satisfies conduction required by a digital processing unit.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US Patent No. 20150179616 A1), Park (US Patent No. 20230014933 A1), and Lee et al (US Patent No. 20110304011 A1) as applied to claim 3 above, in further view of Ha et al. (US Patent No. 20230060946 A1).
Regarding claim 7, Lin et al. disclose the digital processing unit area comprises a plurality of electric connectivity areas filled inside the via holes (263, Fig. 6d, paragraph 91) for electric conduction between the electric connectivity areas and the information connectivity points (432, Fig 10f) of the digital processing unit area (430) (paragraph 126-127)
Park discloses the chip pads (124) may include data pads (information connectivity points) (paragraph 33).
However, the above references do not teach the digital processing unit area comprises a plurality of electric connectivity areas filled inside the via holes for electric conduction.
On the other hand, Ha et al. disclose a connectivity/conduction between the electric connectivity areas (340a) in the via (470) and the information connectivity points (530) (paragraph 72, Fig. 1)
It would have been obvious to one of ordinary skill in the art before the effectively filing date of the claimed invention to modify the above references according to the teachings of Ha et al. such that the information connectivity points are inside the via holes and the connectivity areas are conductive with the information connectivity points. Doing so would provide electric conduction between an electronic component and other electrical components
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US Patent No. 20150179616 A1) and Park (US Patent No. 20230014933 A1), as applied to claim 1 above, in further view of Oh et al. (US Patent No. 20210066204 A1).
Regarding claim 4, Lin et al. do not teach analog processing unit area having an analog processing unit characteristic of electric conduction with the digital processing unit.
However, Oh et al. teach electrical components (121) and (122) can be comprised of digital signal processors or audio (analog) processors and be electrically connected to conductors (112) (paragraph 28, Fig. 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin et al. according to the teachings of Oh et al. so that the digital processing unit and analog processing unit are electrically connected. Doing so would bridge analog data, such as light and sound, with digital processing to allow for storage and manipulation.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (‘616) (US Patent No. 20150179616 A1), Park (US Patent No. 20230014933 A1), and Oh et al. (US Patent No. 20210066204 A1) as applied to claim 4 above, in further view of Lin et al. (‘764) (US Patent No. 20210118764 A1).
Regarding claim 6, Lin et al. (‘616) does not disclose the analog processing unit area comprises an analog signal transmitter unit and an analog signal receiver unit, each of which is characteristic of electric conduction with the analog processing unit.
However, Lin et al. (‘764) disclose an integrated device (202) may include a transmitter and receiver that are interconnected. (paragraph 25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the arts cited above with the teachings of Lin et al. (‘764) such that the analog processing unit area comprises of a signal transmitter and a signal receiver that are electrically connected. Doing so would allow the analog transmitter and receiver to establish a common ground reference point.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/STEVE PHAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817