DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/31/2025 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 7-8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suthiwongsunthorn et al. (PG Pub. No. US 2015/0357256 A1, hereinafter referenced as ‘Suth’)
Regarding claim 1, Suth teaches a semiconductor device (10), comprising:
an integrated circuit (¶ 0015: die circuitry connected to die pads) formed on a front side of a semiconductor substrate (¶ 0015: circuits at least indirectly formed on surface 110a);
a first dielectric layer (¶ 0018: 150) directly on a sidewall of a semiconductor material of the semiconductor substrate (¶ 0019 & fig. 1c among others: 150 formed directly on sidewall 110c or 110d of die 110, which is formed of semiconductor material); and
a second dielectric layer (¶ 0020: polymer layer 140) on a back side of the semiconductor substrate opposite to the front side (fig. 1c: 140 disposed on back side 110b of semiconductor die 110), the second dielectric layer discontinuous from the first dielectric layer (fig. 1c: at least a portion of 140 is discontinuous from 150),
wherein the first and second dielectric layers share a vertical interface coplanar with the sidewall of the semiconductor material of the semiconductor device (fig. 1c: 150 and 140 share a vertical interface coplanar with 110c or 110d).
Regarding claim 3, Suth teaches the semiconductor device of claim 1, wherein:
the first dielectric layer includes a first dielectric material (¶ 0018); and
the second dielectric layer includes a second dielectric material different from the first dielectric material (¶ 0020: 140 comprises different material from 150).
Regarding claim 7, Suth teaches a semiconductor device (¶ 0023 & fig. 1i: 26), comprising:
an integrated circuit (¶ 0014: circuit components) formed on a front side of a semiconductor substrate (¶ 0014: circuit components formed at least indirectly on front side 110a of die 110; since 110 is singulated from semiconductor substrate 210, it meets the broadest reasonable interpretation of ‘semiconductor substrate’);
a first dielectric layer (¶ 0020: 140) on a back side of the semiconductor substrate opposite to the front side (fig. 1i: 140 disposed on back side 110b of die 110); and
a second dielectric layer (¶ 0018: 150) directly on a sidewall of a semiconductor material of the semiconductor substrate (fig. 1i: 150 disposed on sidewalls 110c and 110d of die 110) and directly contacting the first dielectric layer at a substantially vertical interface coplanar with the sidewall of the semiconductor material of the semiconductor device (figs. 1i, 12e among others: 150 directly contacts 140 at a substantially vertical interface coplanar with sidewalls 110c/110d).
Regarding claim 8, Suth teaches the semiconductor device of claim 7, wherein the second dielectric layer is discontinuous from the first dielectric layer (fig. 1c: 150 forms an interface with 140, meeting the broadest reasonable interpretation of ‘discontinuous’).
Regarding claim 10, Suth teaches the semiconductor device of claim 7, wherein:
the first dielectric layer includes a first dielectric material (¶ 0018); and
the second dielectric layer includes a second dielectric material different from the first dielectric material (¶ 0020: 140 comprises different material from 150).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (PG Pub. No. US 2018/0166396 A1) in view of Suth.
Regarding claim 1, Lee teaches a semiconductor device (fig. 5C), comprising:
an integrated circuit formed on a front side of a semiconductor substrate (¶ 0020: active elements formed on surface 100A of substrate portion 100’);
a first dielectric layer (¶¶ 0030, 0092: 160 and/or 155’) on a sidewall of the semiconductor substrate (fig. 5C among others: 155’/160 formed directly on sidewall of 100’); and
an adhesive layer (¶ 0038: 190) on a back side of the semiconductor substrate opposite to the front side (fig. 5C: at least a portion of 190 formed on a back side of 100’), the adhesive layer discontinuous from the first dielectric layer (fig. 5C: 190 forms an interface with 155/’160, meeting the broadest reasonable interpretation of ‘discontinuous’).
Lee does not teach the material of the adhesive layer comprises a second dielectric, or wherein the first and second dielectric layers share a vertical interface coplanar with the sidewall of the semiconductor material of the semiconductor device.
Suth teaches a semiconductor device (figs. 1g, 12e: package 26) wherein a second dielectric layer (¶ 0020: 140) disposed on a back side of a semiconductor substrate opposite to an active front side (¶ 0092 & figs. 1g, 12a: 140 formed on a back side of 110), the second dielectric layer discontinuous from a first dielectric layer (¶¶ 0018-0020 & fig. 12c: 140 forms an interface with 150, meeting the broadest reasonable interpretation of ‘discontinuous’), wherein the first and second dielectric layers share a vertical interface coplanar with the sidewall of the semiconductor material of the semiconductor device (see annotated fig. 1c below: in at least one embodiment, interface of 140 and 150 coplanar with sidewall 110c or 110d of 110).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the adhesive of Lee with dielectric material, as a means to provide a protective film suitable for use in a die pick process (Suth, ¶ 0088, Lee, ¶ 0039). In addition, configuring an interface of first and second dielectric layers (150/140 of Suth, 160/190 of Lee) to be vertically coplanar with the semiconductor device sidewall would allow for singulation through a single dielectric material (Suth, fig. 12d: singulation process penetrates/divides encapsulant 250 but does not penetrate 140), improving manufacturing efficiency.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, the material of Suth is suitable to provide the adhesive layer of Lee.
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Regarding claim 2, Lee in view of Suth teaches the semiconductor device of claim 1, wherein the first dielectric layer includes at least two dielectric materials (Lee, ¶ 0030: 155’/160).
Regarding claim 3, Lee in view of Suth teaches the semiconductor device of claim 1, wherein:
the first dielectric layer includes a first dielectric material (Lee, ¶¶ 0030, 0083); and
the second dielectric layer includes a second dielectric material different from the first dielectric material (155’/160 of Lee comprises different material than 140 of Suth).
Regarding claim 7, Lee teaches a semiconductor device, comprising:
an integrated circuit formed on a front side of a semiconductor substrate (¶ 0020 & fig. 5C: active and passive elements formed at least indirectly on surface 100B of substrate 100’);
an adhesive layer (¶ 0037: 190) on a back side of the semiconductor substrate opposite to the front side (fig. 5C: 190 disposed on back side 100B of 100’); and
a second dielectric layer (¶¶ 0030, 0091: 155’ and/or 160) directly on a sidewall of a semiconductor material of the semiconductor substrate and directly contacting the first dielectric layer at a substantially vertical interface coplanar with the sidewall of the semiconductor material of the semiconductor device (fig. 5C: 155’/160 formed on a sidewall of 100’ and directly contacts sidewall of 100’).
Lee does not teach the material of the adhesive layer comprises a first dielectric.
Suth teaches a semiconductor device (fig. 1c among others) wherein a first dielectric layer (¶ 0020: 140) is disposed on a back side of a semiconductor substrate opposite to an active front side (fig. 3e: 140 formed on a back side of 110), the first dielectric layer discontinuous from a second dielectric layer (¶ 0018 & fig. 1c: at least a bottom portion of 140 discontinuous from dielectric 150).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the adhesive of Lee with dielectric material, as a means to provide a protective film suitable for use in a die pick process (Suth, ¶ 0088, Lee, ¶ 0039).
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, the material of Suth is suitable to provide the adhesive layer of Lee.
Regarding claim 8, Lee in view of Suth teaches the semiconductor device of claim 7, wherein the second dielectric layer is discontinuous from the first dielectric layer (Lee, fig. 5C: 190, as modified to include the dielectric material of Suth, forms an interface with 155’/160, meeting the broadest reasonable interpretation of ‘discontinuous’).
Regarding claim 9, Lee in view of Suth teaches the semiconductor device of claim 7, wherein the second dielectric layer includes at least two dielectric materials (Lee, ¶ 0030: 160 includes a multilayer structure, and/or comprises fillers).
Regarding claim 10, Lee in view of Suth teaches the semiconductor device of claim 7, wherein:
the first dielectric layer includes a first dielectric material (Suth, ¶ 0020: 190 comprises resin); and
the second dielectric layer includes a second dielectric material different from the first dielectric material (155’/160 of Lee is different from 140 of Suth).
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Suth as applied to claims 3 and 10 above, and further in view of Chen et al. (PG Pub. No. US 2020/0091090 A1).
Regarding claim 4, Lee in view of Suth teaches the semiconductor device of claim 3, wherein the first dielectric material includes an oxide, a nitride, an oxynitride, or a combination thereof (Lee, ¶ 0091: 155’ comprises oxide).
Lee in view of Suth does not teach the second dielectric material includes an oxide, a nitride, an oxynitride, or a combination thereof.
Chen teaches a semiconductor device (fig. 2: 400) including a second dielectric layer (¶ 0012: 104, similar to 190 of Lee and/or 140 of Suth) on a back side of a semiconductor substrate (fig. 2 among others: 140 disposed on back side of 105a/105b), the second dielectric material including an oxide, a nitride, an oxynitride, or a combination thereof (¶ 0012: 104 includes oxide and/or nitride).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the second dielectric material of Lee in view of Suth with an oxide or nitride, as a means to reduce coefficient of thermal expansion (CTE) mismatch and a local warpage of the semiconductor dies (Chen, ¶ 0013).
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, the material of Chen is suitable to provide the second dielectric material of Lee and Suth.
Regarding claim 11, Lee in view of Suth teaches the semiconductor device of claim 10, wherein the second dielectric material includes an oxide, a nitride, an oxynitride, or a combination thereof (Lee, ¶ 0092: 155’ includes oxide).
Lee in view of Suth does not teach the first dielectric material includes an oxide, a nitride, an oxynitride, or a combination thereof.
Chen teaches a semiconductor device (fig. 2: 400) including a first dielectric layer (¶ 0012: 104, similar to 190 of Lee and/or 140 of Suth) on a back side of a semiconductor substrate (fig. 2 among others: 140 disposed on back side of 105a/105b), the first dielectric material including an oxide, a nitride, an oxynitride, or a combination thereof (¶ 0012: 104 includes oxide and/or nitride).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first dielectric material of Lee in view of Suth with an oxide or nitride, as a means to reduce coefficient of thermal expansion (CTE) mismatch and a local warpage of the semiconductor dies (Chen, ¶ 0013).
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, the material of Chen is suitable to provide the first dielectric material of Lee and Suth.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Suth as applied to claims 3 and 10 above, and further in view of Han et al. (PG Pub. No. US 2021/0013181 A1).
Regarding claim 5, Lee in view of Suth teaches the semiconductor device of claim 1, comprising a second dielectric material (Suth, 160) on the back side of a substrate (Suth, fig. 1C). Lee in view of Suth further teaches one or more electrical connectors (Lee, ¶ 0026: 140) for the integrated circuit (Lee, fig. 5C: 140 provides electrical connection to circuits of 100’).
Lee in view of Suth does not teach the semiconductor device further comprising:
one or more vias extending from the front side of the semiconductor substrate past the second dielectric material on the back side, the one or more vias coupled with the integrated circuit and configured to provide one or more electrical connections for the integrated circuit on a surface of the second dielectric material.
Han teaches a semiconductor device (fig. 1: 10) including one or more vias (¶ 0017: 110) extending from a front side of a semiconductor substrate past a second dielectric material on the back side (fig. 1: 110 extends from a front side of 101, similar to 110’ of Lee, past a dielectric material 101b on a back side), the one or more vias coupled with an integrated circuit (¶ 0017: 110 coupled with semiconductor device of 101) and configured to provide one or more electrical connections for the integrated circuit on a surface of the second dielectric material (¶ 0026: 110 configured to provide electrical connections 111 and/or 130 for 101 on a surface of 101b).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Lee with the vias of Han, as a means to provide an upper semiconductor package stably mounted on a lower semiconductor package or a package in which an upper semiconductor package is electrically connected to a substrate (Han, ¶ 0004), reducing size and improving productivity of the package (Han, ¶ 0039).
Regarding claim 12, Lee in view of Suth teaches the semiconductor device of claim 10, comprising a second dielectric material (Lee, 190 and/or Suth, 140) on the back side of a substrate (Lee, fig. 1G and/or Suth, fig. 1c).
Lee in view of Suth does not teach the semiconductor device further comprising:
one or more vias extending from the front side of the semiconductor substrate past the second dielectric material on the back side, the one or more vias coupled with the integrated circuit and configured to provide one or more electrical connections for the integrated circuit on a surface of the second dielectric material.
Han teaches a semiconductor device (fig. 1: 10) including one or more vias (¶ 0017: 110) extending from a front side of a semiconductor substrate past a first dielectric layer on the back side (fig. 1: 110 extends from a front side of 101, similar to 110’ of Lee, past a dielectric material 101b on a back side), the one or more vias coupled with an integrated circuit (¶ 0017: 110 coupled with semiconductor device of 101) and configured to provide one or more electrical connections for the integrated circuit on a surface of the second dielectric material (¶ 0026: 110 configured to provide electrical connections 111 and/or 130 for 101 on a surface of 101b).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor device of Lee in view of Suth with the vias of Han, as a means to provide an upper semiconductor package stably mounted on a lower semiconductor package or a package in which an upper semiconductor package is electrically connected to a substrate (Han, ¶ 0004), reducing size and improving productivity of the package (Han, ¶ 0039).
Response to Arguments
1. Applicant’s arguments, see page 5, filed 12/17/2025, with respect to the 35 USC § 112(b) rejection of claim 12 have been fully considered and are persuasive. Accordingly, the 35 USC § 112(b) rejection of claim 12 has been withdrawn.
2. Applicant’s arguments with respect to the 35 USC § 102 and/or 35 USC § 103 rejections of claims 1-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Furthermore, in response to applicant's arguments against the references individually (“Suthiwongsunthorn does not remedy this deficiency of Lee, nor would a person skilled in the art be motivated to modify Lee or Suthiwongsunthorn to include this feature”), one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Scanlan et al. (US 2015/0187710 A1) teaches a semiconductor device (176) including a first dielectric layer (50) and a second dielectric layer (62) sharing a vertical interface coplanar with a sidewall of semiconductor material of a semiconductor device (fig. 6: 50 and 62 share a vertical; interface coplanar with side surface of 24).
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/BRIAN TURNER/Examiner, Art Unit 2818
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