Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 22 is objected to because of the following informalities: the limitation of “wherein the interposer comprises a lower insulation layer; and an upper metal layer“ has already been disclosed in claim 10 of which claim 22 is dependent on. Therefore the rejection of claim 22 below will continue with the removal of the repeated limitation. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US-20150035129-A1 referred as Zhang) in view of Hartung et al. (US-20230014380-A1 referred as Hartung) and Kim (US-20170278830-A1).
Regarding claim 1. Zhang discloses a semiconductor package comprising:
a lead frame comprising a first die paddle; and a second die paddle ([0018-0019], figure 1c, a lead frame comprising of a first die paddle #12 and a second die paddle #11);
a low side field-effect transistor (FET) being flipped and attached to the first die paddle ([0018-0019], figure 1c, a low side FET #30 is seen flipped and attached to the first die paddle #12. Please note the conductive adhesive #91 therein between is used as a way to keep both elements #30 and #12 attached and electrically connected), the low side FET comprising a source electrode and a gate electrode on a top surface of the low side FET; and a drain electrode on a bottom surface of the low side FET ([0018-0019], figure 1c, the low side FET #30 further includes a top surface of a source electrode #S2 and gate electrode #G2 facing downwards due to the flipping of the low side FET #30. Furthermore, the drain electrode #D2 is seen facing upwards in respect to the flipping as well);
a high side FET attached to the second die paddle ([0018-0019], figure 1c, a high side FET #20 is seen attached to the second die paddle #11. Please note the conductive adhesive #91 therein between is used as a way to keep both elements #20 and #11 attached and electrically connected), the high side FET comprising a source electrode and a gate electrode on a top surface of the high side FET; and a drain electrode on a bottom surface of the high side FET ([0018-0019], figure 1c, the high side FET #20 includes a source electrode #S1 and a gate electrode #G1 on a top surface facing upwards. And further including a drain electrode #D1 on a bottom surface facing downwards);
a metal clip connecting the drain electrode of the low side FET to the source electrode of the high side FET ([0018-0019], figure 1c, a metal clip #40 is seen connecting the drain electrode #D2 of the low side FET #30 to the source electrode #S1 of the high side FET #20. Please note the conductive adhesive #91 therein between is used as a way to keep all three elements #40, #30, and #20 attached and electrically connected); and
a molding encapsulation enclosing the low side FET, the high side FET, and the metal clip ([0018-0019], figure 1c, a molding encapsulation #100 is seen enclosing the low side FET #30, high side FET #20 and the metal clip #40).
Zhang lacks an interposer attached to a top surface of the metal clip;
an integrated circuit (IC) controller attached to a top surface of the interposer; and
a molding encapsulation enclosing the interposer, and the IC controller;
wherein the interposer comprises
a lower insulation layer; and
an upper metal layer;
wherein the upper metal layer of the interposer is electrically connected to a ground terminal; and
wherein the upper metal layer of the interposer provides electromagnetic interference (EMI) and capacitive shielding to the IC controller.
Hartung discloses an interposer attached to a top surface of the metal clip ([0021-0024], figure 1, a interposer #1 is seen attached to a top surface of the metal clip #7. Please note the solder joint layer #8 therein between is used as a way to keep both elements #1 and #7 attached and electrically connected);
an integrated circuit (IC) controller attached to a top surface of the interposer ([0021-0024], figure 1, an integrated circuit #2 is seen attached to a top surface of the interposer #1); and
a molding encapsulation enclosing the interposer and the IC controller ([0025], figure 1, a molding encapsulation #6/#5 is seen enclosing the interposer #1 and the IC controller #2).
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wherein the interposer comprises: a lower insulation layer; and an upper metal layer ([0021], figure 1 annotated above, the interposer #1 further includes an upper metal layer #1b and a lower insulation layer #1-Ins (which is described as being in between the lower metal layer #1a and the upper metal layer #1b which means is the unlabeled element now annotated as #1-Ins)) ;
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang to include an interposer, integrated circuit and a molding encapsulation as taught by Hartung in order to optimize the use of MOSFETS in the circuitry, enhance thermal management, and to reduce overall cost of manufacturing with high performance.
Zhang as modified by Hartung still lacks wherein the upper metal layer of the interposer is electrically connected to a ground terminal; and
wherein the upper metal layer of the interposer provides electromagnetic interference (EMI) and capacitive shielding to the IC controller.
Kim discloses wherein the upper metal layer of the interposer is electrically connected to a ground terminal ([0026], figure 1b, wherein the upper metal layer #200 of the interposer #125G/125S is electrically connected to a ground terminal, as described); and
wherein the upper metal layer of the interposer provides electromagnetic interference (EMI) and capacitive shielding to the IC controller ([0026-0027], figure 1b, the upper metal layer #200 provides electromagnetic interference and capacitive shielding, as described, to the IC controller #1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified by Hartung to further include ground terminal, electromagnetic interference, and capacitive protection as taught by Kim in order to provide additional safety to the device, extend the devices lifetime, and to reduce circuit failures.
Regarding claim 5. Zhang as modified discloses wherein the low side FET and the high side FET are disposed side-by-side ([0018-0019], figure 1c, the low side FET #30 and the high side FET #20 are seen disposed side-by-side).
Regarding claim 7. Zhang as modified discloses wherein the low side FET is a metal-oxide- semiconductor field-effect transistor (MOSFET); and wherein the high side FET is another MOSFET ([0018-0019], figure 1c, both the low side FET #30 and the high side FET #20 are MOSFETS as described).
Regarding claims 8 and 9. Zhang as modified lacks
[claim 8] wherein the interposer covers at least 50% of the top surface of the metal clip.
[claim 9] wherein the interposer covers at least 75% of the top surface of the metal clip.
Hartung discloses
[claim 8] wherein the interposer covers at least 50% of the top surface of the metal clip ([0021], figure 1, the interposer #1 is seen covering at least 79% of the top surface of the metal clip #7).
[claim 9] wherein the interposer covers at least 75% of the top surface of the metal clip ([0021], figure 1, the interposer #1 is seen covering at least 79% of the top surface of the metal clip #7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include further modify the interposer with at least 75% to the metal clip as taught by Hartung in order to promote signal integrity within the device, increase the devices lifetime and to promote the electrical performance.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US-20150035129-A1 referred as Zhang), Hartung et al. (US-20230014380-A1 referred as Hartung) and Kim (US-20170278830-A1), in further view of Kikuchi et al. (US-20230162080-A1 referred as Kikuchi).
Regarding claim 3 and 4. Zhang as modified lacks
[claim 3] further comprising a plurality of bond wires electrically connecting the upper metal layer of the interposer to a power ground terminal.
[claim 4] further comprising a plurality of bond wires electrically connecting the upper metal layer of the interposer to an analog ground terminal.
Kikuchi discloses
[claim 3] further comprising a plurality of bond wires electrically connecting the upper metal layer of the interposer to a power ground terminal ([0079, 0082], figure 1e, a wiring layer #302 (which includes a plurality of wirings) is electrically connecting the upper metal layer #301 of the interposer #30 to a ground terminal #10 (described in [0099, 0118]) by further going through the solder-joined bumps #31. The ground terminal #302 is ‘configured to’ be grounded as applied to them, thus reading on a power ground terminal).
[claim 4] further comprising a plurality of bond wires electrically connecting the upper metal layer of the interposer to an analog ground terminal ([0079, 0082], figure 1e, a wiring layer #302 (which includes a plurality of wirings) is electrically connecting the upper metal layer #301 of the interposer #30 to a ground terminal #10 (described in [0099, 0118]) by further going through the solder-joined bumps #31. The ground terminal #302 is ‘configured to’ be grounded as applied to them, thus reading on a power ground terminal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include a plurality of bond wires electrically connecting the upper metal layer of the interposer to a power/analog ground terminal as taught by Kikuchi in order to promote a safe output of voltage in the device, increase the devices lifetime and to promote the electrical performance.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US-20150035129-A1 referred as Zhang), Hartung et al. (US-20230014380-A1 referred as Hartung) and Kim (US-20170278830-A1), in further view of Gebuhr et al. (US-20230238769-A1 referred as Gebuhr).
Regarding claim 6. Zhang as modified lacks further comprising a plurality of bond wires electrically connecting the IC controller to the lead frame.
Gebuhr discloses further comprising a plurality of bond wires electrically connecting the IC controller to the lead frame ([0069], figure 1c-1d, a plurality of bond wires #80 is seen connected the IC controller #10 to the lead frame #20 as illustrated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include a plurality of bond wires electrically connecting the IC controller to the lead frame as taught by Gebuhr in order to provide a direct connection with no interference, enhance the usability of the device, and to enhance the devices efficiency.
Claims 10, 14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US-20150035129-A1 referred as Zhang) in view of Hartung et al. (US-20230014380-A1 referred as Hartung), Kim (US-20170278830-A1), and Jong et al. (US-20090127685-A1 referred as Jong).
Regarding claim 10. Zhang discloses a method for fabricating a semiconductor package, the method comprising the steps of:
providing a lead frame comprising a first die paddle; and a second die paddle ([0018-0019], figure 1c, a lead frame comprising of a first die paddle #12 and a second die paddle #11);
attaching a low side field-effect transistor (FET) and a high side FET to the first die paddle, and the second die paddle respectively ([0018-0019], figure 1c, a low side FET #30 and high side FET #20 is seen connected to the first die paddle #12 and the second die paddle #11 respectively. Please note the conductive adhesive #91 therein between is used as a way to keep both pairs of its respective elements attached and electrically connected);
mounting a metal clip connecting a drain electrode of the low side FET to a source electrode of the high side FET ([0018-0019], figure 1c, a metal clip #40 is seen connecting the drain electrode #D2 of the low side FET #30 to the source electrode #S1 of the high side FET #20. Please note the conductive adhesive #91 therein between is used as a way to keep all three elements #40, #30, and #20 attached and electrically connected);
forming a molding encapsulation enclosing the low side FET, the high side FET, and the metal clip ([0018-0019], figure 1c, a molding encapsulation #100 is seen enclosing the low side FET #30, high side FET #20 and the metal clip #40); and
wherein the low side FET is flipped ([0018-0019], [0023], figure 1c, the low side FET #30 is flipped as described).
Zhang lacks attaching an interposer to a top surface of the metal clip;
mounting an integrated circuit (IC) controller on a top surface of the interposer;
forming a molding encapsulation enclosing the interposer, and the IC controller;
applying a singulation process so as to separate the semiconductor package from other semiconductor packages.
wherein the interposer comprises
a lower insulation layer; and
an upper metal layer;
wherein the upper metal layer of the interposer is electrically connected to a ground terminal; and
wherein the upper metal layer of the interposer provides electromagnetic interference (EMI) and capacitive shielding to the IC controller.
Hartung discloses attaching an interposer to a top surface of the metal clip ([0021-0024], figure 1, a interposer #1 is seen attached to a top surface of the metal clip #7. Please note the solder joint layer #8 therein between is used as a way to keep both elements #1 and #7 attached and electrically connected);
mounting an integrated circuit (IC) controller on a top surface of the interposer ([0021-0024], figure 1, an integrated circuit #2 is seen attached to a top surface of the interposer #1);
forming a molding encapsulation enclosing the interposer, and the IC controller ([0025], figure 1, a molding encapsulation #6/#5 is seen enclosing the interposer #1 and the IC controller #2).
wherein the interposer comprises a lower insulation layer; and an upper metal layer ([0021], figure 1 annotated above, the interposer #1 further includes an upper metal layer #1b and a lower insulation layer #1-Ins (which is described as being in between the lower metal layer #1a and the upper metal layer #1b which means is the unlabeled element now annotated as #1-Ins));
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang to include a interposer, integrated circuit and a molding encapsulation as taught by Hartung in order to optimize the use of MOSFETS in the circuitry, enhance thermal management, and to reduce overall cost of manufacturing with high performance.
Zhang as modified by Hartung still lacks applying a singulation process so as to separate the semiconductor package from other semiconductor packages, and
wherein the upper metal layer of the interposer is electrically connected to a ground terminal; and
wherein the upper metal layer of the interposer provides electromagnetic interference (EMI) and capacitive shielding to the IC controller.
Jong discloses applying a singulation process so as to separate the semiconductor package from other semiconductor packages ([0014], The singulation process is known in the semiconductor art and is the process where one or more components, which are initially part of a larger entity such as a substrate or wafer, are separated from the larger entity and made into individual entities.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include applying a singulation process as taught by Jong in order to improve the chip yield in number of usable devices, reduce the manufacturing costs, and to ensure each device meets quality standards.
Zhang as modified by Hartung and Jong still lacks wherein the upper metal layer of the interposer is electrically connected to a ground terminal; and
wherein the upper metal layer of the interposer provides electromagnetic interference (EMI) and capacitive shielding to the IC controller.
Kim discloses wherein the upper metal layer of the interposer is electrically connected to a ground terminal ([0026], figure 1b, wherein the upper metal layer #200 of the interposer #125G/125S is electrically connected to a ground terminal, as described); and
wherein the upper metal layer of the interposer provides electromagnetic interference (EMI) and capacitive shielding to the IC controller ([0026-0027], figure 1b, the upper metal layer #200 provides electromagnetic interference and capacitive shielding, as described, to the IC controller #1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to further include ground terminal, electromagnetic interference, and capacitive protection as taught by Kim in order to provide additional safety to the device, extend the devices lifetime, and to reduce circuit failures.
Regarding claim 14. Zhang as modified discloses wherein the low side FET and the high side FET are disposed side- by-side ([0018-0019], figure 1c, the low side FET #30 and the high side FET #20 are seen disposed side-by-side).
Regarding claim 16. Zhang as modified discloses wherein the low side FET is a metal-oxide-semiconductor field- effect transistor (MOSFET); and wherein the high side FET is another MOSFET ([0018-0019], figure 1c, both the low side FET #30 and the high side FET #20 are MOSFETS as described).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US-20150035129-A1 referred as Zhang), Hartung et al. (US-20230014380-A1 referred as Hartung), Kim (US-20170278830-A1), and Jong et al. (US-20090127685-A1 referred as Jong), in further view of Kikuchi et al. (US-20230162080-A1 referred as Kikuchi).
Regarding claim 12 and 13. Zhang as modified lacks
[claim 12] further comprising the step of applying a plurality of bond wires electrically connecting the upper metal layer of the interposer to a power ground terminal.
[claim 13] further comprising the step of applying a plurality of bond wires electrically connecting the upper metal layer of the interposer to an analog ground terminal.
Kikuchi discloses
[claim 12] further comprising the step of applying a plurality of bond wires electrically connecting the upper metal layer of the interposer to a power ground terminal ([0079, 0082], figure 1e, a wiring layer #302 (which includes a plurality of wirings) is electrically connecting the upper metal layer #301 of the interposer #30 to a ground terminal #10 (described in [0099, 0118]) by further going through the solder-joined bumps #31. The ground terminal #302 is ‘configured to’ be grounded as applied to them, thus reading on a power ground terminal).
[claim 13] further comprising the step of applying a plurality of bond wires electrically connecting the upper metal layer of the interposer to an analog ground terminal ([0079, 0082], figure 1e, a wiring layer #302 (which includes a plurality of wirings) is electrically connecting the upper metal layer #301 of the interposer #30 to a ground terminal #10 (described in [0099, 0118]) by further going through the solder-joined bumps #31. The ground terminal #302 is ‘configured to’ be grounded as applied to them, thus reading on a power ground terminal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include a plurality of bond wires electrically connecting the upper metal layer of the interposer to a power/analog ground terminal as taught by Kikuchi in order to promote a safe output of voltage in the device, increase the devices lifetime and to promote the electrical performance.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US-20150035129-A1 referred as Zhang), Hartung et al. (US-20230014380-A1 referred as Hartung), Kim (US-20170278830-A1), and Jong et al. (US-20090127685-A1 referred as Jong), in further view of Gebuhr et al. (US-20230238769-A1 referred as Gebuhr).
Regarding claim 15. Zhang as modified lacks further comprising applying a plurality of bond wires electrically connecting the IC controller to the lead frame
Gebuhr discloses further comprising applying a plurality of bond wires electrically connecting the IC controller to the lead frame ([0069], figure 1c-1d, a plurality of bond wires #80 is seen connected the IC controller #10 to the lead frame #20 as illustrated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include a plurality of bond wires electrically connecting the IC controller to the lead frame as taught by Gebuhr in order to provide a direct connection with no interference, enhance the usability of the device, and to enhance the devices efficiency.
Claim 17-18 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US-20150035129-A1 referred as Zhang) in view of Hartung et al. (US-20230014380-A1 referred as Hartung).
Regarding claim 17, Zhang discloses a semiconductor package comprising:
a lead frame comprising a first die paddle; and a second die paddle ([0018-0019], figure 1c, a lead frame comprising of a first die paddle #12 and a second die paddle #11);
a low side field-effect transistor (FET) being flipped and attached to the first die paddle ([0018-0019], figure 1c, a low side FET #30 is seen flipped and attached to the first die paddle #12. Please note the conductive adhesive #91 therein between is used as a way to keep both elements #30 and #12 attached and electrically connected), the low side FET comprising a source electrode and a gate electrode on a top surface of the low side FET; and a drain electrode on a bottom surface of the low side FET ([0018-0019], figure 1c, the low side FET #30 further includes a top surface of a source electrode #S2 and gate electrode #G2 facing downwards due to the flipping of the low side FET #30. Furthermore, the drain electrode #D2 is seen facing upwards in respect to the flipping as well);
a high side FET attached to the second die paddle ([0018-0019], figure 1c, a high side FET #20 is seen attached to the second die paddle #11. Please note the conductive adhesive #91 therein between is used as a way to keep both elements #20 and #11 attached and electrically connected), the high side FET comprising a source electrode and a gate electrode on a top surface of the high side FET; and a drain electrode on a bottom surface of the high side FET ([0018-0019], figure 1c, the high side FET #20 includes a source electrode #S1 and a gate electrode #G1 on a top surface facing upwards. And further including a drain electrode #D1 on a bottom surface facing downwards);
a metal clip connecting the drain electrode of the low side FET to the source electrode of the high side FET ([0018-0019], figure 1c, a metal clip #40 is seen connecting the drain electrode #D2 of the low side FET #30 to the source electrode #S1 of the high side FET #20. Please note the conductive adhesive #91 therein between is used as a way to keep all three elements #40, #30, and #20 attached and electrically connected); and
a molding encapsulation enclosing the low side FET, the high side FET, and the metal clip ([0018-0019], figure 1c, a molding encapsulation #100 is seen enclosing the low side FET #30, high side FET #20 and the metal clip #40).
Zhang lacks an interposer attached to a top surface of the metal clip;
an integrated circuit (IC) controller attached to a top surface of the interposer; and
a molding encapsulation enclosing the interposer, and the IC controller.
Hartung discloses an interposer attached to a top surface of the metal clip ([0021-0024], figure 1, a interposer #1 is seen attached to a top surface of the metal clip #7. Please note the solder joint layer #8 therein between is used as a way to keep both elements #1 and #7 attached and electrically connected);
an integrated circuit (IC) controller attached to a top surface of the interposer ([0021-0024], figure 1, an integrated circuit #2 is seen attached to a top surface of the interposer #1); and
a molding encapsulation enclosing the interposer and the IC controller ([0025], figure 1, a molding encapsulation #6/#5 is seen enclosing the interposer #1 and the IC controller #2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang to include a interposer, integrated circuit and a molding encapsulation as taught by Hartung in order to optimize the use of interposers in the circuitry, enhance thermal management, and to reduce overall cost of manufacturing with high performance.
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Regarding claim 18. Zhang as modified lacks wherein the interposer comprises a lower insulation layer; and an upper metal layer.
Hartung discloses wherein the interposer comprises a lower insulation layer; and an upper metal layer ([0021], figure 1 annotated above, the interposer #1 further includes an upper metal layer #1b and a lower insulation layer #1-Ins (which is described as being in between the lower metal layer #1a and the upper metal layer #1b which means is the unlabeled element now annotated as #1-Ins)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang to include wherein the interposer comprises a lower insulation layer; and an upper metal layer as taught by Hartung in order to optimize the use of interposers in the circuitry, enhance thermal management, and to reduce overall cost of manufacturing with high performance.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US-20150035129-A1 referred as Zhang) and Hartung et al. (US-20230014380-A1 referred as Hartung) in further view of Ko et al. (US-10410993-B2 referred as Ko).
Regarding claim 19. Zhang as modified lacks a non-conductive epoxy,
wherein the lower insulation layer of the interposer is directly attached to the non-conductive epoxy; and
wherein the non-conductive epoxy is directly attached to the metal clip.
Ko discloses a non-conductive epoxy,
wherein the lower insulation layer of the interposer is directly attached to the non-conductive epoxy ([0034], figure 2F, the interposer #110 is a multilayered structure which contains the lower insulation layer #111 as described in [0030] at figure 2c. The non-conductive epoxy #114 is seen directly attached to the interposer #110 on the insulation layer #111 within); and
wherein the non-conductive epoxy is directly attached to the metal clip ([0032], figure 2F, the nonconductive epoxy #114 is seen directly attached to the metal clip #113).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include a nonconductive epoxy directly attached to the interposer and the metal clip as taught by Hartung in order to enhance the direct contact between two elements, reduce device failure from falling apart, and to extend the devices lifetime.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US-20150035129-A1 referred as Zhang) and Hartung et al. (US-20230014380-A1 referred as Hartung) in further view of Rosenberg et al. (US-20160315448-A1 referred as Rosenberg).
Regarding claim 20. Zhang as modified lacks wherein the interposer is of a first rectangular prism shape, wherein the lower insulation layer is of a second rectangular prism shape, and wherein the upper metal layer is of a third rectangular prism shape.
Rosenberg discloses wherein the interposer is of a first rectangular prism shape, wherein the lower insulation layer is of a second rectangular prism shape, and wherein the upper metal layer is of a third rectangular prism shape ([0018-0019], figure 1, the interposer #72 can be shaped of a rectangular prism shape, as described. And since the interposer contains both isolating material (lower insulation layer) and conductive material (upper metal layer), both of materials would also be in a rectangular prism shape).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include the interposer having a rectangular prism shape as taught by Rosenberg in order to improve the devices design, reduce total weight in the device, and to reduce material used in manufacturing.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US-20150035129-A1 referred as Zhang) and Hartung et al. (US-20230014380-A1 referred as Hartung) in further view of Kim et al. (US-20190287951-A1 referred as Kim #2).
Regarding claim 21. Zhang as modified lacks wherein a thickness of the lower insulation layer is at least ten times of a thickness of the upper metal layer.
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Figure 7B annotated
Kim #2 discloses wherein a thickness of the lower insulation layer is at least ten times of a thickness of the upper metal layer ([0090], figure 7b annotated above, seen in the thickness perspective of #View1, the thickness of the lower insulation layer #610 is at least ten times than the thickness of the uppermetal layers #630S/630G).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include wherein a thickness of the lower insulation layer is at least ten times of a thickness of the upper metal layer as taught by Kim #2 in order to provide additional insulating protection, distribute the weight of the device, and to enhance electrical safety.
Claims 22 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US-20150035129-A1 referred as Zhang), Hartung et al. (US-20230014380-A1 referred as Hartung), Kim (US-20170278830-A1), and Jong et al. (US-20090127685-A1 referred as Jong) as applied to claim 10, in further view of Ko et al. (US-10410993-B2 referred as Ko).
Regarding claim 22. Zhang as modified lacks wherein the semiconductor package comprises a non-conductive epoxy, wherein the lower insulation layer of the interposer is directly attached to the non- conductive epoxy; and wherein the non-conductive epoxy is directly attached to the metal clip.
Ko discloses wherein the semiconductor package comprises a non-conductive epoxy, wherein the lower insulation layer of the interposer is directly attached to the non- conductive epoxy ([0034], figure 2F, the interposer #110 is a multilayered structure which contains the lower insulation layer #111 as described in [0030] at figure 2c. The non-conductive epoxy #114 is seen directly attached to the interposer #110 on the insulation layer #111 within); and wherein the non-conductive epoxy is directly attached to the metal clip ([0032], figure 2F, the nonconductive epoxy #114 is seen directly attached to the metal clip #113).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Zhang as modified to include a nonconductive epoxy directly attached to the interposer and the metal clip as taught by Ko in order to enhance the direct contact between two elements, reduce device failure from falling apart, and to extend the devices lifetime.
Response to Amendment
Applicant's arguments filed 03/26/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art by new prior art. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
Furthermore, the applicant argues that the combination of Zhang et al. and Hartung et al. are respectfully traversed since both inventions contain circuits that are different ,therefore, a person of ordinary skill in the art would not be motivated to include the interposer from Hartungs reference to be attached to Zhangs reference. The argument is that it would be reasonable in certain instances to include the interposer with the Low and High side field effect transistors such as allowing for denser interconnects, improved power efficiency, and enhanced power distribution.
36. Regarding elements 3B and 3C of claim 17 on pg 8-10 of the arguments, applicant argues about claim 17 (originally claim 1) not having a reasonable combination as noted in arguments 3a, 3b, and 3c. In response to argument 3a, the semiconductor transistor die #2, which is a transistor broadly has a control aspect (the gate input is a control input to control what happens with the source and drain) therefore it can be considered as an integrated circuit controller. Applicant is invited to amend the claims to provide a more specific structure to overcome this interpretation. In response to argument 3b, the applicant recites that the secondary reference Hartung discloses multiple molding encapsulations of #5 and #6 rather than just one as claimed but the first potting material #5 and the second potting material #6 together together would form as one molding encapsulation which encloses the interposer #1 and the IC controller #2, regardless if the material is slightly different since claim 17 does not further limit the material of the molding encapsulation. The claim language would need to be made more specific in order to overcome this interpretation. In response to argument 3c, the applicant argues a person of ordinary skill would not have been motivated to combine an interposer to Zhangs reference, but instead it would be obvious in certain instances to include an interposer such as thermal management or aiding in creating a more efficient FET when combined.
37. Regarding element 3A of claim 18 on pg 10, applicant argues about claim 18 (originally claim 2) not including the insulative layer. More specifically, the applicant recites that the secondary reference, Hartung, not having the correct structural limitation from claim 18 as the insulating layer is described as being in between the multiple metal layers within the interposer. The examiner disagrees as the insulating layer is unlabeled but described as being in between the metal layers 1a/1b/1c. The annotated figure 1 seen above emphasizes the exact placement of the unlabeled insulating layer to show that figure 1 does in fact contain the insulating layer #1-Ins. Therefore the claim 18 language mapping of the upper metal layer #1B and the lower insulating layer #1-Ins meets the limitation and remains true. Furthermore, the applicant has added claims 19-22 which is stated in the new rejection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action (noting that new claims 17 and 18 which were original claims 1 and 2 were rejected with the same references as in the previous office action). Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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