DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I claims 1-10 in the reply filed on 02/17/2026 is acknowledged.
Amended claim 11 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: Amendment to claim 11 creates antecedent basis issues for the lower electrode. Group II which consists of claims 11-17 still includes a transistor which is not present in Group I
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 11-17 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2022-0139113, filed on 10/26/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/15/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The specific feature “the second lower electrode is located on an upper end portion of the second lower electrode,” is indefinite and may refer to a protruding portion of the second electrode but this is unclear.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102 as being anticipated by Cho et al. ( US 2021/0202490 A1; hereinafter Cho )
Regarding claim 1, Cho teaches a semiconductor device ( Fig. 1: integrated circuit device ) comprising: a lower structure ( Fig. 2: a lower structure 11 ); lower electrodes ( Fig. 2: storage node electrodes 40 and 80 ) on the lower structure ( Fig. 2 #11 ), wherein each lower electrode ( [0023} storage node electrodes 40 and 80 ) includes a first lower electrode ( Fig. 2 #40 ) and a second lower electrode ( Fig. 2 #80 ) on the first lower electrode ( Fig. 2 #40 ) and electrically connected to the first lower electrode ( [0025] The top sub-electrode 80 may contact the bottom sub-electrode 40 and may be electrically connected thereto ); an upper electrode ( Fig. 2: plate electrode 100 ) covering the lower electrodes ( Fig. 2 #40 ); and a dielectric film ( Fig. 2: dielectric layer 90 ) between the lower electrodes ( Fig. 2 #40 and #80 ) and the upper electrode ( Fig. 2 #100; [0029] The dielectric layer 90 may be disposed on the storage node electrodes 40 and 80; [0031] The plate electrode 100 may be disposed on the dielectric layer 90 ), wherein the first lower electrode ( Fig. 2 #40 ) includes a pillar portion ( [0024] The storage node electrodes 40 and 80 may have a pillar shape ), and a protruding portion on the pillar portion ( top of electrode structure in Fig. 2 ), wherein the protruding portion extends upward from the pillar portion with a width gradually decreasing ( Fig. 3B 41a-u ), and contacts the second lower electrode ( Fig. 3B #81b-d ).
Regarding claim 2, Cho teaches the semiconductor device of claim 1 ( as discussed above), wherein the protruding portion has a conical shape ( Fig. 3B #41a-u ), and wherein the conical shape includes a shape having a constantly inclined side surface ( as shown in Fig. 3B ), a shape having a region of which a lateral slope varies in a height direction, or a shape of which a lateral slope entirely varies in the height direction ( as shown in Fig. 3B ).
Regarding claim 3, Cho teaches the semiconductor device of claim 1 ( as discussed above), wherein a width of the protruding portion gradually decreases as a distance from the lower structure increases ( Fig. 3B #41 a-u; [0034] A minimum width wu of the upper portion 41a-u including the recess RC may be narrower than a maximum width wd of a top end of the lower portion 41a-d ).
Regarding claim 4, Cho teaches the semiconductor device of claim 1 ( as discussed above), wherein at least a portion of an upper surface of the protruding portion ( Fig. 3B #41 a-u ) contacts ( first lower electrode contacts first upper electrode; see drawing objections above ) the second lower electrode ( Fig. 3B #81 b-d ).
Regarding claim 5, Cho teaches the semiconductor device of claim 1 ( as discussed above), wherein at least a portion of the second lower electrode does not vertically overlap the first lower electrode ( Fig. 3B #81a-u does not overlap #41a-u ).
Regarding claim 6, Cho teaches the semiconductor device of claim 1 ( as discussed above ), further comprising: an etch stop layer ( Fig. 15 upper etch stop layer 50 ) having a conformal thickness ( [0075] The upper etch stop layer 50 may include a filler part 50a which covers a top surface of each of the second lower supporter pattern 39 and the bottom sub-electrode 40 and partially fills the opening portion OP. The filler part 50a may be formed to cover the inclined surface SS of the bottom sub-electrode 40 and the exposed portion of the third bottom mold layer 25, in the opening portion OP ) and extending horizontally to surround at least a portion of a side surface of the protruding portion ( as shown in Fig. 15 ).
Regarding claim 7, Cho teaches the semiconductor device of claim 6 ( as discussed above), wherein a lower surface of the second lower electrode ( Fig. 22 #81a ) is covered by the protruding portion ( Fig. 22 #41a ) and the etch stop layer (Fig. 22 #50 ).
Regarding claim 8, Cho teaches the semiconductor device of claim 6 ( as discussed above), wherein the etch stop layer ( Fig. 2 #90 ) comprises at least one of SiN, SiCN, or SiBN ( [0075] the upper etch stop layer 50 may include bowing block SiN (B—SiN) or bowing block SiON (B—SiON)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under U.S.C. 103 as being unpatentable over Cho et al.; US 2021/0202490 A1; 07/2020 in view of Park; US 2020/0350264 A1; 11/2018
Claim 9: Cho discloses the semiconductor device of claim 1 ( as discussed above).
Cho discloses a second protruding portion having a conical shape ( Fig. 2: top of 81a ).
Cho does not appear to disclose each of the lower electrodes further comprises a third lower electrode on the second lower electrode and electrically connected to the second lower electrode.
However, Park teaches each of the lower electrodes ( Fig. 35: M1 and M2) further comprises a third lower electrode ( Fig. 35: third lower electrode M1 ) on the second lower electrode ( Fig. 35: second lower electrode M2 ) and electrically connected to the second lower electrode ( [0090] a third via hole for connection between a second lower electrode M2 and the third lower electrode M1 through an etching process ).
This rejection does not address the feature “the second lower electrode is located on an upper end portion of the second lower electrode,” because this portion of the claim is indefinite as discussed in the 112 rejection above.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Park with Cho to implement each of the lower electrodes further comprises a third lower electrode on the second lower electrode and electrically connected to the second lower electrode because this would increase the total surface area and the vertical aspect ratio of the electrode.
Claim 10 is rejected under U.S.C. 103 as being unpatentable over Cho et al.; US 2021/0202490 A1; 07/2020 in view of Park; US 2020/0350264 A1; 11/2018 as it relates to claim 9 and further in view of Seong et al.; US 2017/0271581 A1; 02/2017
Claim 10: Cho and Park disclose the semiconductor device of claim 9 ( as discussed above ).
Neither Cho nor Park appear to disclose in plan view, the third lower electrode has a portion misaligned with the second lower electrode.
However, Seong teaches in plan view, the third lower electrode ( Fig. 4A third electrode 350 ) has a portion misaligned ( as shown in Fig. 4A ) with the second lower electrode ( Fig. 4A second electrode 330 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Seong with Cho and Park to implement in plan view, the third lower electrode has a portion misaligned with the second lower electrode because high aspect ratio etching can lead to tapering between levels.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights