DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8 and 15 are rejected under U.S.C. 103 as being unpatentable over Cho et al.; US 2021/0202490 A1; 07/2020 in view of Song et al.; US 2020/0075674 A1; 03/2019
Claim 1: Cho discloses a semiconductor device ( Fig. 1: integrated circuit device ) comprising: a lower structure ( Fig. 2: a lower structure 11 ); lower electrodes ( Fig. 2: storage node electrodes 40 and 80 ) on the lower structure ( Fig. 2 #11 ), wherein each lower electrode ( [0023} storage node electrodes 40 and 80 ) includes a first lower electrode ( Fig. 2 #40 ) and a second lower electrode ( Fig. 2 #80 ) on the first lower electrode ( Fig. 2 #40 ) and electrically connected to the first lower electrode ( [0025] The top sub-electrode 80 may contact the bottom sub-electrode 40 and may be electrically connected thereto ); an upper electrode ( Fig. 2: plate electrode 100 ) covering the lower electrodes ( Fig. 2 #40 ); and a dielectric film ( Fig. 2: dielectric layer 90 ) between the lower electrodes ( Fig. 2 #40 and #80 ) and the upper electrode ( Fig. 2 #100; [0029] The dielectric layer 90 may be disposed on the storage node electrodes 40 and 80; [0031] The plate electrode 100 may be disposed on the dielectric layer 90 ), wherein the first lower electrode ( Fig. 2 #40 ) includes a pillar portion ( [0024] The storage node electrodes 40 and 80 may have a pillar shape ), and a protruding portion on the pillar portion ( top of electrode structure in Fig. 2 ), wherein the protruding portion extends upward from the pillar portion with a width gradually decreasing ( Fig. 3B 41a-u ), and contacts the second lower electrode ( Fig. 3B #81b-d ).
Cho does not appear to disclose the protruding portion comprises an inclined side surface in contact with the second lower electrode.
However, Song ( ‘674 ) teaches the protruding portion ( Fig. 8A protruding portion LIE a2 ) comprises an inclined side surface ( as shown in Fig. 8A ) in contact with the second lower electrode ( Fig. 8A first upper intermediate electrode UIEa )
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Song (‘674 ) with Cho to implement the protruding portion comprises an inclined side surface in contact with the second lower electrode because this approach is a practical engineering choice to enhance electrical performance, mechanical robustness, and manufacturability.
Claim 2: Cho and Song ( ‘674 ) disclose the semiconductor device of claim 1 ( as discussed above).
Cho teaches the protruding portion has a conical shape ( Fig. 3B #41a-u ), and wherein in the conical shape: the inclined side surface has a constant incline ( as shown in Fig. 3B ), a lateral slope of the inclined side surface varies in a height direction in a region of the conical shape ( lateral slope varies in a height direction as shown in Fig. 3B ), or the lateral slope of the inclined side surface, varies in the height direction ( as shown in Fig. 3B ) for an entire height of the conical shape.
Claim 3: Cho and Song ( ‘674 ) disclose the semiconductor device of claim 1 ( as discussed above).
Cho teaches the width of the protruding portion gradually decreases as a distance from the lower structure increases ( Fig. 3B #41 a-u; [0034] A minimum width wu of the upper portion 41a-u including the recess RC may be narrower than a maximum width wd of a top end of the lower portion 41a-d ).
Claim 5: Cho and Song ( ‘674 ) disclose the semiconductor device of claim 1 ( as discussed above).
Cho teaches at least a portion of the second lower electrode does not vertically overlap the first lower electrode ( Fig. 3B #81a-u does not overlap #41a-u ).
Claim 6: Cho and Song ( ‘674 ) disclose the semiconductor device of claim 1 ( as discussed above ).
Cho teaches an etch stop layer ( Fig. 15 upper etch stop layer 50 ) having a conformal thickness ( [0075] The upper etch stop layer 50 may include a filler part 50a which covers a top surface of each of the second lower supporter pattern 39 and the bottom sub-electrode 40 and partially fills the opening portion OP. The filler part 50a may be formed to cover the inclined surface SS of the bottom sub-electrode 40 and the exposed portion of the third bottom mold layer 25, in the opening portion OP ) and extending horizontally to surround at least a portion of a side surface of the protruding portion ( as shown in Fig. 15 ).
Claim 7: Cho and Song ( ‘674 ) disclose the semiconductor device of claim 6 ( as discussed above).
Cho teaches a lower surface of the second lower electrode ( Fig. 22 #81a ) is covered by the protruding portion ( Fig. 22 #41a ) and the etch stop layer (Fig. 22 #50 ).
Claim 8: Cho and Song ( ‘674 ) disclose the semiconductor device of claim 6 ( as discussed above).
Cho teaches the etch stop layer ( Fig. 2 #90 ) comprises at least one of SiN, SiCN, or SiBN ( [0075] the upper etch stop layer 50 may include bowing block SiN (B—SiN) or bowing block SiON (B—SiON)).
Claim 15: Cho and Song ( ‘674 ) disclose the semiconductor device of claim 1 ( as discussed above ).
Cho does not appear to disclose the protruding portion decreases in planar area in a direction, away from the pillar portion of the first lower electrode in a vertical direction, and wherein a lower end of the second lower electrode is located on a level higher than the pillar portion.
However, Song ( ‘674 ) teaches the protruding portion ( Fig. 8A: LIE a2 ) decreases in planar area in a direction, away ( as shown in Fig. 8A ) from the pillar portion ( Fig. 8A: LIE a1 ) of the first lower electrode in a vertical direction ( as shown in Fig. 8A ), and wherein a lower end of the second lower electrode ( Fig. 8A: UIEa ) is located on a level higher than the pillar portion ( [0060] The protruding portion LIEa2 of the first lower intermediate electrode LIEa may be surrounded by the first upper intermediate electrode UIEa ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Song (‘674 ) with Cho to implement the protruding portion decreases in planar area in a direction, away from the pillar portion of the first lower electrode in a vertical direction, and wherein a lower end of the second lower electrode is located on a level higher than the pillar portion because this design strategy ensures the device simultaneously achieves high electrical reliability, manufacturability, and optical/electrical performance.
Claim 9 is rejected under U.S.C. 103 as being unpatentable over Cho et al.; US 2021/0202490 A1; 07/2020 in view of Song et al.; US 2020/0075674 A1; 03/2019 as it relates to claim 1 above and further in view of Park; US 2020/0350264 A1; 11/2018 and Jeong et al.; US 2017/0200676 A1; 12/2016
Claim 9: Cho and Song ( ‘674 ) disclose the semiconductor device of claim 1 ( as discussed above).
Cho discloses the second lower electrode ( Fig. 2 #80 ) has a second protruding portion having a conical shape ( Fig. 2: top of 81a ).
Cho does not appear to disclose each of the lower electrodes further comprises a third lower electrode on the second lower electrode and electrically connected to the second lower electrode, and wherein the third lower electrode is located on an upper end portion of the second lower electrode.
Park discloses each of the lower electrodes ( Fig. 35: M1 and M2) further comprises a third lower electrode ( Fig. 35: third lower electrode M1 ) on the second lower electrode ( Fig. 35: second lower electrode M2 ) and electrically connected to the second lower electrode ( [0090] a third via hole for connection between a second lower electrode M2 and the third lower electrode M1 through an etching process )
Park does not appear to disclose the third lower electrode is located on an upper end portion of the second lower electrode, and wherein the second lower electrode has a second protruding portion having a conical shape, wherein the third lower electrode is located on an upper end portion of the second lower electrode
Jeong teaches the third lower electrode ( Fig. 6 third lower electrode 10c ) is located on an upper end portion ( [0078] the second lower electrode 10b may include a protrusion portion PP that protrudes from the first extension portion EXP1 in the first direction D1 ) of the second lower electrode ( Fig. 6 second lower electrode 10b ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Jeong with Cho, Song (‘674 ), and Park to implement the third lower electrode is located on an upper end portion of the second lower electrode, and wherein the second lower electrode has a second protruding portion having a conical shape, wherein the third lower electrode is located on an upper end portion of the second lower electrode because this would increase the total surface area and the vertical aspect ratio of the electrode.
Claim 10 is rejected under U.S.C. 103 as being unpatentable over Cho et al.; US 2021/0202490 A1; 07/2020, Song et al.; US 2020/0075674 A1; 03/2019, Park; US 2020/0350264 A1; 11/2018, and Jeong et al.; US 2017/0200676 A1; 12/2016 as it relates to claim 9 and further in view of Seong et al.; US 2017/0271581 A1; 02/2017
Claim 10: Cho, Song ( ‘674 ), Park, and Jeong disclose the semiconductor device of claim 9 ( as discussed above ).
Neither Cho nor Song (‘674) nor Park nor Jeong appear to disclose in plan view, the third lower electrode has a portion misaligned with the second lower electrode.
However, Seong teaches in plan view, the third lower electrode ( Fig. 4A third electrode 350 ) has a portion misaligned ( as shown in Fig. 4A ) with the second lower electrode ( Fig. 4A second electrode 330 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Seong with Cho, Song ( ‘674 ), Park, and Jeong to implement in plan view, the third lower electrode has a portion misaligned with the second lower electrode because high aspect ratio etching can lead to tapering between levels.
Claim 11 is rejected under U.S.C. 103 as being unpatentable over Cho et al.; US 2021/0202490 A1; 07/2020 and Song et al.; US 2020/0075674 A1; 03/2019 as it relates to claim 1 and further in view of Morooka; US 2023/0276630 A1; 08/2022 and Goo et al.; US 2023/0207388 A1; 08/2022
Claim 11: Cho and Song ( ‘674 ) disclose the semiconductor device of claim 1 ( as discussed above ).
Cho discloses the protruding portion of the first lower electrode ( Fig. 3 #41a ) has a conical shape ( Fig. 3B #41a-u ), located in an upper end portion of the first lower electrode ( as shown in Fig. 3B ), and extending in a vertical direction ( as shown in Fig. 3B ), perpendicular to the upper surface of the lower structure ( Fig. 2 #11 ), and wherein a vertical central axis of the second lower electrode ( Fig. 3C #81b ) is misaligned with and in contact with a vertical central axis of the first lower electrode ( Fig. 3C #41b ) on the etch stop layer ( Fig. 22 upper etch stop layer 50 ).
Neither Cho nor Song (‘674 ) appear to disclose the semiconductor device includes an upper structure on the lower structure, wherein the upper structure includes: the upper electrode; at least one support layer contacting the lower electrodes and extending in a horizontal direction, parallel to an upper surface of the lower structure; and an etch stop layer on an uppermost support layer among the at least one support layer and extending in the horizontal direction.
Morooka discloses the semiconductor device includes an upper structure ( Fig. 1 upper structure 80 ) on the lower structure ( Fig. 1 lower structure 20 ), wherein the upper structure includes: the upper electrode ( Fig. 1 bit line BL ); at least one support layer ( Fig. 1 stacked body 30 ) contacting the lower electrodes ( Fig. 1 source lines SL ) and extending in a horizontal direction ( as shown in Fig. 1 ), parallel to an upper surface of the lower structure ( as shown in Fig. 1 ).
Morooka does not appear to disclose an etch stop layer on an uppermost support layer among the at least one support layer and extending in the horizontal direction.
Goo discloses an etch stop layer on an uppermost support layer among the at least one support layer ( [0108] Referring to FIGS. 12A and 12B, in the resultant structure of FIGS. 11A, 11B, and 11C, a portion of each of the plurality of insulating films 132 and the plurality of sacrificial insulating films 134 may be removed from the connection region CON of the chip region CR with an etch stop film (not shown) covering an uppermost one of the plurality of insulating films 132 as an etch mask ) and extending in the horizontal direction ( as shown in Fig. 12A ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Goo with Cho, Song ( ‘674 ), and Morooka to implement the semiconductor device includes an upper structure on the lower structure, wherein the upper structure includes: the upper electrode; at least one support layer contacting the lower electrodes and extending in a horizontal direction, parallel to an upper surface of the lower structure; and an etch stop layer on an uppermost support layer among the at least one support layer and extending in the horizontal direction because the inclusion of an upper structure on a lower part of the semiconductor chip serves to stack electrical functionality, shield delicate connections, and enable high-density 3D integration.
Claims 12 and 16 are rejected under U.S.C. 103 as being unpatentable over Cho et al.; US 2021/0202490 A1; 07/2020, in view of Song et al.; US 2020/0075674 A1; 03/2019, Morooka; US 2023/0276630 A1; 08/2022 and Goo et al.; US 2023/0207388 A1; 08/2022 as it relates to claim 11 above and further in view of Youtsey et al.; US 2019/0088495 A1; 07/2018
Claim 12: Cho, Song ( ‘674 ), Morooka, and Goo disclose the semiconductor device of claim 11 ( as discussed above).
Neither Cho nor Song (‘674 ) nor Morooka nor Goo appear to disclose a thickness of the etch stop layer is thinner than a thickness of each of the at least one support layer.
However, Youtsey teaches a thickness of the etch stop layer ( [0091] In some embodiments, the etch stop layer 120 has a thickness in a range from 20 nm to 50 nm ) is thinner than a thickness of each of the at least one support layer ( [0097] In an example embodiment, a thickness of the support layer is between approximately 10 1 μm and 50 μm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Youtsey with Cho, Song ( ‘674 ), Morooka, and Goo to implement a thickness of the etch stop layer is thinner than a thickness of each of the at least one support layer because this arises from optical and carrier-confinement needs, functional design requirements, and mechanical and stress optimization.
Claim 16: Cho, Song ( ‘674 ), Morooka, and Goo disclose the semiconductor device of claim 11 ( as discussed above).
Neither Cho nor Song ( ‘674 ) nor Morooka nor Goo appear to disclose each of the at least one support layer is spaced apart from the etch stop layer.
However, Youtsey teaches each of the at least one support layer ( Fig. 2 #130 ) is spaced apart from the etch stop layer ( Fig. 2 #120 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Youtsey with Cho, Song ( ‘674 ), Morooka, and Goo to implement each of the at least one support layer is spaced apart from the etch stop layer because this approach is used to provide electrical isolation, thermal management, and improve device performance.
Claim 13 is rejected under U.S.C. 103 as being unpatentable over Cho et al.; US 2021/0202490 A1; 07/2020, in view of Song et al.; US 2020/0075674 A1; 03/2019, Morooka; US 2023/0276630 A1; 08/2022 and Goo et al.; US 2023/0207388 A1; 08/2022 as it relates to claim 11 above and further in view of Lo et al.; US 2023/0061501 A1; 08/2021
Claim 13: Cho, Song ( ‘674 ), Morooka, and Goo disclose the semiconductor device of claim 11 ( as discussed above).
Neither Cho nor Song ( ‘674 ) nor Morooka nor Goo appear to disclose the at least one support layer comprises SiN or SiCN, and wherein the etch stop layer comprises at least one of SiN, SiCN, or SiBN.
However, Lo teaches the at least one support layer comprises SiN or SiCN ( [0027] the support layer 222 includes SiO, SiCO, SiNO, SiCN, or SiCON ), and wherein the etch stop layer comprises at least one of SiN, SiCN, or SiBN ( [0041] the second etch stop layer 240 may include a silicon-containing material, such as SiCO, SiCN, SiN, SiCON, SiO.sub.x, SiC, SiON, or the like).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lo with Cho, Song ( ‘674 ), Morooka, and Goo to implement the at least one support layer comprises SiN or SiCN, and wherein the etch stop layer comprises at least one of SiN, SiCN, or SiBN because these materials combine mechanical durability, chemical resistance, high dielectric strength, and surface passivation.
Claim 14 is rejected under U.S.C. 103 as being unpatentable over Cho et al.; US 2021/0202490 A1; 07/2020, in view of Song et al.; US 2020/0075674 A1; 03/2019, Morooka; US 2023/0276630 A1; 08/2022 and Goo et al.; US 2023/0207388 A1; 08/2022 as it relates to claim 11 above and further in view of Jao et al.; US 2023/0420566 A1; 08/2022
Claim 14: Cho, Song ( ‘674 ), Morooka, and Goo disclose the semiconductor device of claim 11 ( as discussed above ).
Neither Cho nor Song ( ‘674 ) nor Morooka nor Goo appear to disclose the etch stop layer surrounds at least a portion of a side surface of the protruding portion.
However, Jao teaches the etch stop layer ( Fig. 2B: first etch stop layer (ESL) 269 ) surrounds at least a portion of a side surface of the protruding portion ( bottom surface of Fig. 2B S/D electrodes 260 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Jao with Cho, Song ( ‘674 ), Morooka, and Goo to implement the etch stop layer surrounds at least a portion of a side surface of the protruding portion because this is a deliberate design strategy to protect conductor sidewalls during via etching, prevent formation of metallic polymers, and ensure structural integrity and mechanical support for thin, high-aspect-ratio features.
Claim 17 is rejected under U.S.C. 103 as being unpatentable over Cho et al.; US 2021/0202490 A1; 07/2020, in view of Song et al.; US 2020/0075674 A1; 03/2019, Morooka; US 2023/0276630 A1; 08/2022, Goo et al.; US 2023/0207388 A1; 08/2022 and Youtsey et al.; US 2019/0088495 A1; 07/2018 as it relates to claim 16 above and further in view of Song et al.; US 2023/0215910 A1; 07/2022
Claim 17: Cho, Song ( ‘674 ), Morooka, Goo, and Youtsey disclose the semiconductor device of claim 16 ( as discussed above ).
Neither Chong nor Song ( ‘674 ) nor Morooka nor Goo nor Youtsey appear to disclose the upper electrode comprises a portion filling between the at least one support layer and the etch stop layer.
However, Song ( ‘910 ) teaches the upper electrode ( Fig. 3H: upper electrode 24 ) comprises a portion ( portion of 24 shown in Fig. 3H on the left and right side of the center portion of 24 ) filling between the at least one support layer ( Fig. 3H lower-level supporter 16S ) and the etch stop layer ( Fig. 3H
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Song (‘910 ) with Cho, Song ( ‘674 ), Morooka, Goo, and Youtsey to implement the upper electrode comprises a portion filling between the at least one support layer and the etch stop layer because this approach improves electrical uniformity, capacitance control, plasma/process uniformity, mechanical and thermal stability, and prevents defects.
Response to Amendment/Arguments
Applicant’s arguments, see page 1 of remarks, filed 06/18/2026, with respect to Restriction of claims 11-17 have been fully considered and are persuasive. The Restriction of claims 11-17 of 12/16/2025 has been withdrawn.
Applicant’s arguments, see page 2 of remarks, filed 06/18/2026, with respect to 35 U.S.C.112 rejection of claim 9 have been fully considered and are persuasive. The 35 U.S.C. 112 rejection of claim 9 on 04/08/2026 has been withdrawn.
Applicant’s arguments, see page 2 of remarks, filed 06/18/2026, with respect to the rejection(s) of claims 1-8 and 9-10 under 35 U.S.C. 102(a)(2) and 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Song ( ‘674 ).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.N.F./Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
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