Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/368,646 filed on 09/15/2023.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 9, 12 and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a lateral surface of the first semiconductor substrate” in lines 22-24.
Claim 26 recites “outer lateral surface of the first semiconductor substrate” in lines 18-21. However, the specification does not define the term “lateral surface” and “outer lateral surface” nor does it provide sufficient description or figures from which the scope of this term can be reasonably ascertained.
At best, the specification discloses “an outer edge of the semiconductor substrate” but, it is unclear whether Applicant was intended for an outer edge instead of lateral surface or outer lateral surface.
It is also unclear whether the recited “lateral surface” refers to a sidewall surface of the semiconductor substrate, an edge portion of an active surface, a peripheral region of the substrate, or some other surface. As a result, it is unclear how the “first through vias” are “arranged in at least two columns that extend along” the lateral surface, or how the spacing “from the device region toward the lateral surface” is to be determined.
Because the boundaries and meaning of the term “lateral surface of the first semiconductor substrate” are unclear, a person of ordinary skill in the art would not be able to determine the scope of claim 1 with reasonable certainty. Therefore, claim 1 is indefinite.
Claim 1 recites the limitation "the first through via" in lines 10-11, 18 and 21. There is insufficient antecedent basis for this limitation in the claim. It appears that Applicant was intended for - - the plurality of first through vias- - or - - the first through via of the plurality of first through vias- -.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 26 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub #2024/0371711 to Chen et al. (Chen).
Regarding independent claim 26, Chen discloses a semiconductor package (Fig. 10: 900), comprising:
a package substrate (Fig. 10: 4 and ¶0041); and
a chip package (Fig. 10: 10 and ¶0042) mounted on the package substrate (4),
wherein the chip package (10) includes:
a semiconductor chip (1) that includes a silicon substrate and a circuit wiring pattern (14) on the silicon substrate (1), the silicon substrate (1) having a semiconductor element (Fig. 10: 54; Under BRI, a “semiconductor element” broadly encompasses any element formed using semiconductor devices or circuitry that performs an electrical function. An amplifier is typically implemented using transistors (MOSFETs, BJTs, etc.) formed on an active surface (12 and ¶0042) of the silicon substrate (1), and the circuit wiring pattern (14) being connected (connected via 57, 58 and 34) to the semiconductor element (54);
a first redistribution layer (2) disposed on a first surface of the semiconductor chip (10); the first surface being directed toward the package substrate (4);
a second redistribution layer (3) disposed on a second surface of the semiconductor chip (1), the second surface being opposite to the first surface; and
a plurality of through vias (13) that vertically penetrate the semiconductor chip (1) and connect the first redistribution layer (2) and the second redistribution layer (3) to each other,
wherein the through vias (13, see Examiner’s Mark-up below) are positioned between the circuit wiring pattern (14) and an outer lateral surface (see above 112 second rejection regarding outer lateral surface) of the silicon substrate (1), and wherein a distance from the outer lateral surface of the silicon substrate (1) to a conductive pattern (Fig. 10: 25) of the first redistribution layer (2) is less than a distance from the outer lateral surface of the silicon substrate to the circuit wiring pattern (14) (see Examiner’s Mark-up below in view of the 112 second rejection regarding outer lateral surface). It is noted that the distance from the outer surface of the silicon substrate (see Examiner’s Mark-up below) to a conductive pattern 25 is less than a distance from the outer surface of the silicon substrate to the circuit wiring layer 14 (see Examiner’s Mark-up below).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2024/0178114 to Suk et al. (Suk) in view of US Pub # 2024/0136311 to Jeon et al. (Jeon).
Regarding independent claim 1, Suk discloses a semiconductor package (Fig. 23), comprising:
a first semiconductor substrate (see Fig. 8: base layer 210 ¶0091 and ¶0032 with respect to Fig. 23) that has a device region and an edge region (see Examiner’s Mark-up below);
a first semiconductor element (¶0032; an integrated element or integrated circuits formed in a lower portion of the first base layer (semiconductor substrate) 210) on the device region, wherein the first semiconductor element is formed on an active surface of the first semiconductor substrate (¶0032);
a first circuit layer (Fig. 23: 220 and ¶0031) disposed on the active surface of the first semiconductor substrate;
a first redistribution layer (Fig. 23: 100) disposed on the first circuit layer; and
a plurality of first through vias (240) on the edge region, wherein the first through vias (240) vertically penetrate the first semiconductor substrate (Fig. 23: 210) and are connected to the first redistribution layer (100), wherein the first circuit layer (220) includes:
a first device interlayer dielectric layer (222 and ¶0033) that covers the active surface of the first semiconductor substrate (210); and
a first circuit wiring pattern (224) on the device region, wherein the first circuit wiring pattern (224) is provided in the first device interlayer dielectric layer (222) and connected to the first semiconductor element (¶0032), wherein the first circuit wiring pattern (224) and the first through vias (240) are electrically connected, and wherein the first through vias (240) are arranged in at least two columns (see Examiner’s Mark-up) that extend along a lateral surface of the first semiconductor substrate (210) and that are spaced apart from each other in a direction from the device region toward the lateral surface of the first semiconductor substrate (both end of the sidewalls 210 are presently considered to be the lateral surface of the semiconductor substrate).
Suk fails to explicitly disclose wherein the plurality of first through vias vertically penetrate the first circuit layer and wherein the first circuit wiring pattern and the first through vias are electrically connected through the first redistribution layer.
Jeon discloses wherein the plurality of first through vias (Fig. 14: 130) vertically penetrate the first circuit layer (Fig. 14: 120) and wherein the first circuit wiring pattern (124) and the first through vias (130) are electrically connected through the first redistribution layer.
¶0064 of Jeon discloses pads 160s are electrically connected to the semiconductor element 122 by coupling pads 160s to wiring pattern 128 and connected through the circuit layer 120 to the semiconductor element 122. (It is noted that the combinations of the protection layer 170 which is SiO and pads 160s which is copper are presently considered to be the first redistribution layer, and it is well-known in the art that a redistribution layer in semiconductor packaging is primarily a metal layer, but it is always used together with dielectric layers).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify the circuit layer of Suk by penetrating the through vias as taught by Jeon in order to be connected to top surfaces of portions of the under-pad pattern (¶0063).
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Regarding claim 2, Suk discloses a semiconductor package including first through vias and a first circuit wiring pattern as recited in claim 1 above.
Although Suk does not expressly state that, when viewed in a plan view, the first through vias are spaced apart from the first circuit wiring pattern, it would have been obvious to one of ordinary skill in the art at the time of the invention to arrange the through vias such that they are laterally spaced apart from the circuit wiring pattern in a plan view, in a direction from the device region toward the edge region. Such an arrangement represents a routine layout modification that improves routing flexibility, reduces electrical interference, and avoids physical overlap between vertical vias and lateral wiring patterns, all of which are recognized design considerations in semiconductor packaging.
Regarding claim 3, Suk discloses wherein the first circuit wiring pattern.
Suk fails to disclose wherein the first circuit wiring pattern is not provided on the edge region.
Jeon discloses wherein the first circuit wiring pattern (Fig. 14: 124) is not provided on the edge region (SCR region). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to replace the circuit layer of Suk with the circuit layer as taught by Jeon in order to reduce damage during dicing, improve manufacturing yield, and enhance reliability by avoiding edge-related defects, which are well-known considerations in semiconductor packaging. Therefore, modifying the circuit wiring pattern of Suk to not be provided on the edge region, as taught by Jeon would have been obvious.
Regarding claim 4, Suk discloses wherein the first through vias vertically penetrate the first semiconductor substrate (Fig. 23: 210).
Suk fails to disclose wherein the first through vias vertically penetrate the first device interlayer dielectric layer.
Jeon discloses wherein the first through vias (Fig. 14: 130) vertically penetrate the first device interlayer dielectric layer (Fig. 14: 120).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the device interlayer dielectric layer of Suk by vertically penetrating the through vias as taught by Jeon in order to be connected to top surfaces of portions of the under-pad pattern (¶0063).
Regarding claim 5, Suk discloses a first area of the device region and a second area of the edge region (see Examiner’s Mark-up above from claim 1).
Although Suk does not explicitly disclose a ratio in the range of about 5:95 to about 95:5, it would have been obvious to one of ordinary skill in the art to optimize the relative area of the device and edge regions to achieve a ratio within the claimed range. Such optimization of area ratios is a routine design consideration in semiconductor packaging to balance layout density, improve manufacturability, and ensure reliable edge clearance. Therefore, selecting a ratio within the claimed range would have been an obvious matter of optimization. MPEP 2144.05
Regarding claim 9, Suk discloses a second redistribution layer (Fig. 23: 600) disposed on an inactive surface of the first semiconductor substrate (210), wherein the first through vias (240) connect the first redistribution layer (100) and the second redistribution layer (600) to each other.
Regarding claim 12, Suk discloses a plurality of pads (Fig. 23: 120) disposed on the first redistribution layer (100), wherein at least one of the pads is positioned on the edge region (see Examiner’s Mark-up above from claim 1).
Claims 13-19 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2024/0178114 to Suk et al. (Suk) in view of US Pub # 2024/0136311 to Jeon et al. (Jeon).
Regarding independent claim 13, Chen discloses a semiconductor package (Fig. 10), comprising:
a first semiconductor chip (Fig. 10: 10 see ¶0042) that includes a first silicon substrate (Fig. 10: 1), a first semiconductor element (Fig. 10: 54; Under BRI, a “semiconductor element” broadly encompasses any element formed using semiconductor devices or circuitry that performs an electrical function. An amplifier is typically implemented using transistors (MOSFETs, BJTs, etc.) and integrated semiconductor circuitry) formed on an active surface of the first silicon substrate (1), and a first circuit layer (Fig. 10: 14 and ¶0042) disposed on the active surface of the first silicon substrate (1);
a first redistribution layer (Fig. 10: 3) disposed on an active surface of the first semiconductor chip (10) and coupled to the first circuit layer (14);
a second redistribution layer (Fig. 10: 2) disposed on an inactive surface of the first semiconductor chip (10);
a first through via (Fig. 10: 13 and ¶0046) that vertically penetrates the first semiconductor chip (10) and connects the first redistribution layer (3) and the second redistribution layer (2) to each other; and
a plurality of pads (Fig. 10: 34 and ¶0072) disposed on the first redistribution layer (3),
wherein the first through via (Fig. 10: 13) is spaced apart from the first circuit wiring pattern (14).
Chen fails to explicitly disclose wherein the first circuit layer includes a first device interlayer dielectric layer that covers the active surface of the first silicon substrate; and a first circuit wiring pattern provided in the first device interlayer dielectric layer.
Jeon discloses wherein the first circuit layer (Fig. 14: 120 and ¶0064) includes a first device interlayer dielectric layer (126; ¶0056) that covers the active surface of the first silicon substrate (110) and a first circuit wiring pattern (124, ¶0056) provided in the first device interlayer dielectric layer (126).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify the circuit layer of Chen to include a first device interlayer dielectric layer and a first circuit wiring pattern in order to provide an electrical connection between signal pads and the circuit layer (¶0028).
Regarding claim 14, Chen discloses wherein the first silicon substrate (1) includes a device region on which the first semiconductor element (54) is provided and an edge region that surrounds the device region, and the first through via (13) is disposed on the edge region.
Chen fails to explicitly disclose the first circuit wiring pattern is provided on the device region.
Jeon discloses the first circuit wiring pattern (Fig. 11: 124) is provided on the device region (DR).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the device region of Chen with the first circuit wiring pattern (124) as taught by Jeon in order to provide an electrical connection between signal pads and the circuit layer (¶0028).
Regarding claim 15, Chen in view of the Jeong discloses wherein the first circuit wiring pattern (14) is not provided on the edge region.
Regarding claim 16, Chen discloses wherein at least one of the pads (34) is positioned on the edge region.
Regarding claim 17, Chen in view of the Jeong discloses wherein the first circuit wiring pattern (14) and the first through via (13) are electrically connected through the first redistribution layer (3).
Regarding claim 18, Chen discloses all of the claimed limitations of claim 13 from which this claim depends. Chen discloses wherein the first through vias (13) vertically penetrate the first silicon substrate (1).
Chen fails to explicitly disclose wherein the first through vias vertically penetrate first device interlayer dielectric layer.
Jeon discloses wherein the first through vias (130) vertically penetrate the first device interlayer dielectric layer (126).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the silicon substrate of Chen to include the first device interlayer dielectric layer as taught by Jeon in order to provide an electrical connection between signal pads and the circuit layer (¶0028).
Regarding claim 19, Chen discloses a semiconductor package including first through vias extending through a semiconductor substrate (Fig. 10: 13]). The reference further teaches arranging the through vias with spacing between adjacent vias as part of the package layout.
Although Chen does not explicitly disclose that each of a width of the first through vias and an interval between the first through vias is in a range of about 0.001 mm to about 1 mm, the width of through vias and the spacing (interval) between through vias are recognized result-effective variables in semiconductor packaging. It would have been obvious to one of ordinary skill in the art at the time of the invention to optimize the via width and via interval within a predictable range, such as the claimed range, to balance current-carrying capability, routing density, and mechanical reliability, which are routine design considerations in semiconductor package fabrication.
Accordingly, selecting a via width and via interval within the claimed range represents an obvious matter of optimization of known parameters, rendering this claim obvious over Chen. MPEP 2144.05
Regarding claim 25, Chen discloses a package substrate (Fig. 10: 4) mounted on the first redistribution layer (2) through a plurality of connection terminals (454) provided on the pads (452) and a third semiconductor chip (¶0002, see Fig. 10: 10 multiple integrated circuit, ¶0042) on the package substrate and horizontally spaced apart from the first semiconductor chip (Fig. 10).
Allowable Subject Matter
Claims 21-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 21 recites:
a second semiconductor chip mounted on the second redistribution layer, wherein the second semiconductor chip includes a second silicon substrate, a second semiconductor element formed on an active surface of the second silicon substrate, and a second circuit layer disposed on the active surface of the second silicon substrate; a third redistribution layer disposed on an active surface of the second semiconductor chip and coupled to the second circuit layer; a fourth redistribution layer disposed on an inactive surface of the second semiconductor chip; and a second through via that vertically penetrates the second semiconductor chip and connects the third redistribution layer and the fourth redistribution layer to each other.
The above recitations, interpreted in combination with all other limitations of the claim and all limitations of any claims they depend from, is not taught or rendered obvious by the prior art of record and are indicated as allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub # 2021/0343547 to Chang et al., US Pub 2021/0375773 to Lee et al., US Pub #2021/0366834 to Kim et al., US Pub # 2015/0145055 to Kim., US Pub # 2009/0305502 to Lee et al., US Pub # 2021/0407962 to Kim et al.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896