DETAILED ACTION
This Action is responsive to the Amendment filed on 04/29/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 11, and 12 are rejected under 35 U.S.C. 102(1)(a) as being anticipated by Jan (US 2014/0035081).
Regarding claim 1, Jan (see, e.g., FIG. 6) discloses a semiconductor packaging assembly comprising:
a circuit board 209a comprising a first surface e.g., top of 209a, a second surface e.g., bottom of 209a facing away from the first surface e.g., top of 209a, at least one receiving hole e.g., space between portions of 209a recessed from the first surface e.g., top of 209a toward the second surface e.g., bottom of 209a, each of the at least one receiving hole e.g., space between portions of 209a having a same size, and a plurality of first welding pads 208 on the first surface e.g., top of 209a (Para 0044, Para 0048);
at least one chip 206 received in the at least one receiving hole e.g., space between portions of 209a and spaced apart from the circuit board 209a by a gap e.g., lateral space between 206 and 209a, wherein each of the at least one chip 206 comprises an active surface e.g., top of 206 facing away from the second surface e.g., bottom of 209a, a passive surface e.g., bottom of 206 facing away from the active surface e.g., top of 206, and a plurality of pins 207 arranged on the active surface e.g., top of 206 (Para 0037);
a packaging body 210, 220 in the gap e.g., lateral space between 206 and 209a and bonded to the at least one chip 206 and the circuit board 209a, the packaging body 210, 220 further covering the passive surface e.g., bottom of 206 of the at least one chip 206 (Para 0036, Para 0044); and
wires 205 attached to a third surface e.g., top surface of 220 (e.g., option where 220 partially covers 205) of the packaging body 210, 220 facing away from the second surface e.g., bottom of 209a, and each of the wires 205 electrically connected to at least one of the plurality of pins 207 and at least one of the plurality of first welding pads 208 (Para 0037, Para 0044).
Regarding claim 2, Jan (see, e.g., FIG. 6) teaches the semiconductor packaging assembly of claim 1, wherein the plurality of first welding pads 208 is arranged at an edge of the first surface e.g., top of 209a close to the at least one chip 206, the plurality of pins 207 is arranged at an edge of the active surface e.g., top of 206, and each of the plurality of pins 207 is adjacent to one of the plurality of first welding pads 208.
Regarding claim 11, Jan (see, e.g., FIG. 6) discloses an opto-electromechanical device comprising:
a semiconductor packaging assembly 300 comprising:
a circuit board 209a comprising a first surface e.g., top of 209a, a second surface e.g., bottom of 209a facing away from the first surface e.g., top of 209a, at least one receiving hole e.g., space between portions of 209a recessed from the first surface e.g., top of 209a toward the second surface e.g., bottom of 209a, each of the at least one receiving hole e.g., space between portions of 209a having a same size, and a plurality of first welding pads 208 on the first surface e.g., top of 209a (Para 0044, Para 0048);
at least one chip 206 received in the at least one receiving hole e.g., space between portions of 209a and spaced apart from the circuit board 209a by a gap e.g., lateral space between 206 and 209a, wherein each of the at least one chip 206 comprises an active surface e.g., top of 206 facing away from the second surface e.g., bottom of 209a and a passive surface e.g., bottom of 206 facing away from the active surface e.g., top of 206, a plurality of pins 207 arranged on the active surface e.g., top of 206 (Para 0037, Para 0044);
a packaging body 210, 220 in the gap e.g., lateral space between 206 and 209a and bonded to the at least one chip 206 and the circuit board 209a, the packaging body 210, 220 further covering the passive surface e.g., bottom of 206 of the at least one chip 206 (Para 0036, Para 0044); and
wires 205 attached to a third surface e.g., top of 220 (e.g., option where 220 partially covers 205) of the packaging body 210, 220 facing away from the second surface e.g., bottom of 209a, and each of the wires 205 electrically connected to at least one of the plurality of pins 207 and at least one of the plurality of first welding pads 208 (Para 0037, Para 0044).
Regarding claim 12, Jan (see, e.g., FIG. 6) teaches opto-electromechanical device of claim 11, wherein the plurality of first welding pads 208 is arranged at an edge of the first surface e.g., top of 209a close to the at least one chip 206, the plurality of pins 207 is arranged at an edge of the active surface e.g., top of 206, and each of the plurality of pins 207 is adjacent to one of the plurality of first welding pads 208.
Claims 1, 5, 11, and 15 are rejected under 35 U.S.C. 102(1)(a) as being anticipated by Hu (US 2016/0212851).
Regarding claim 1, Hu (see, e.g., FIG. 3’) discloses semiconductor packaging assembly comprising:
a circuit board 20, 27 (see also FIG. 2A) comprising a first surface 20a, a second surface 20b facing away from the first surface 20a, at least one receiving hole 300 recessed from the first surface 20a toward the second surface 20b, each of the at least one receiving hole 300 having a same size, and a plurality of first welding pads 280 on the first surface 20a (Para 0059, Para 0084, Para 0087);
at least one chip 23 received in the at least one receiving hole 300 and spaced apart from the circuit board 20, 27 by a gap e.g., lateral space between 23 and 20, 27, wherein each of the at least one chip 23 comprises an active surface e.g., top of 23 facing away from the second surface 20b, a passive surface 23b facing away from the active surface e.g., top of 23, and a plurality of pins 280 arranged on the active surface e.g., top of 23 (Para 0084, Para 0085, Para 0087);
a packaging body 33, 39 in the gap e.g., lateral space between 23 and 20, 27 and bonded to the at least one chip 23 and the circuit board 20, 27, the packaging body 33, 39 further covering the passive surface e.g., 23b of the at least one chip 23 (Para 0085, Para 0087); and
wires 38a attached to a third surface e.g., top of 39 of the packaging body 33, 39 facing away from the second surface 20b, and each of the wires 38a electrically connected to at least one of the plurality of pins 280 and at least one of the plurality of first welding pads 280’ (Para 0085-Para 0087).
Regarding claim 5, Hu (see, e.g., FIG. 3’) teaches the semiconductor packaging assembly of claim 1, further comprising an insulating layer 31 covering the wires 38a and bonded to the third surface e.g., top of 39, wherein the wires 38a are located between the insulating layer 31 and the third surface e.g., top of 39 (Para 0087).
Regarding claim 11, Hu (see, e.g., FIG. 3’) teaches an opto-electromechanical device comprising:
a semiconductor packaging assembly 3’ comprising (Para 0083):
a circuit board 20, 27 (see also FIG. 2A) comprising a first surface 20a, a second surface 20b facing away from the first surface 20a, at least one receiving hole 300 recessed from the first surface 20a toward the second surface 20b, each of the at least one receiving hole 300 having a same size, and a plurality of first welding pads 280’ on the first surface 20a (Para 0059, Para 0084, Para 0087);
at least one chip 23 received in the at least one receiving hole 300 and spaced apart from the circuit board 20, 27 by a gap e.g., lateral space between 23 and 20, 27, wherein each of the at least one chip 23 comprises an active surface e.g., top of 23 facing away from the second surface 20b and a passive surface 23b facing away from the active surface e.g., top of 23, a plurality of pins 280 arranged on the active surface e.g., top of 23 (Para 0084, Para 0085, Para 0087);
a packaging body 33, 39 in the gap e.g., lateral space between 23 and 20, 27 and bonded to the at least one chip 23 and the circuit board 20, 27, the packaging body 33, 39 further covering the passive surface e.g., 23b of the at least one chip 23 (Para 0087); and
wires 38a attached to a third surface e.g., top of 39 of the packaging body 33, 39 facing away from the second surface 20b, and each of the wires 38a electrically connected to at least one of the plurality of pins 280 and at least one of the plurality of first welding pads 280’ (Para 0085-Para 0087).
Regarding claim 15, Hu (see, e.g., FIG. 3’) teaches opto-electromechanical device of claim 11, further comprising an insulating layer 31 covering the wires 38a and bonded to the third surface e.g., top of 39, wherein the wires 38a are located between the insulating layer 31 and the third surface e.g., top of 39 (Para 0087).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 2016/0212851), in view of Hatano (US 2021/0313367).
Regarding claim 18, although Hu (FIG. 3’) shows substantial features of the claimed invention, Hu (FIG. 3’) fails to expressly teach an optical element.
Hu (see, e.g., FIG. 5’) teaches an optical element 50 (Para 0098-Para 0101). Hatano (see, e.g., FIG. 1), on the other hand, teaches that the optical element 7 allows various types of light incident from an optical system, such as a lens, generally positioned above the glass to pass through to convey the light to the light-receiving surface of the image sensor (Para 0080).
The combination of Hu (see, e.g., FIG. 3’) / Hu (see, e.g., FIG. 5’) teaches the opto-electromechanical device of claim 11, further comprising an optical element 50 (as taught by Hu, FIG. 5’) and a colloid 31 (as taught by Hu, FIG. 3’), wherein the optical element 50 (as taught by Hu, FIG. 5’) is bonded to a junction of the circuit board 20, 27 (as taught by Hu, FIG. 3’) and the at least chip 23 (as taught by Hu, FIG. 3’) through the colloid 31 (as taught by Hu, FIG. 3’), and the optical element 50 (as taught by Hu, FIG. 5’) is spaced apart from the at least one chip 23 (as taught by Hu, FIG. 3’).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the optical element of Hu (FIG. 5’) to the device of Hu (FIG. 3’) for the purpose of allowing various types of light incident from an optical system, such as a lens, generally positioned above the glass to pass through to convey the light to the light-receiving surface of the image sensor (Para 0080).
Allowable Subject Matter
Claims 8-10 are allowed.
Claims 3 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 04/29/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues that the Office Action alleges that the chip 206 of Jan is analogous to the chip of claim 1, and that the adhesion layer 210, 220 of Jan is analogous to the packaging body of claim 1. However, from FIG. 6 of Jan, the adhesion layer 210, 220 does not cover the passive surface (the lower surface) of the chip 206. Therefore, Jan fails to disclose, teach, or suggest the above-emphasized features of "the packaging body further covering the passive surface of the at least one chip", (emphasized added) as recited in amended claim 1.
Examiner responds:
The Examiner respectfully disagrees. The Jan reference, see, e.g., FIG. 6, shows that packaging body indicated as the combines structure of 210, 220 covers the passive surface (the lower surface) of the chip 206.
Applicant argues:
Applicant argues that the Office Action alleges that the electronic element 23 of Hu is analogous to the chip of claim 1, and that the bonding layer 39 of Hu is analogous to the packaging body of claim 1. However, from FIG. 3' of Hu, the bonding layer 39 does not cover the passive surface (the lower surface) of the electronic element 23. Therefore, Hu fails to disclose, teach, or suggest the above-emphasized features of "the packaging body further covering the passive surface of the at least one chip", (emphasized added) as recited in amended claim 1.
Examiner responds:
The Examiner respectfully disagrees. The Hu reference, see, e.g., FIG. 3’, shows that the packaging body indicated as the combined structure of 33, 39 covers the passive surface (the lower surface) of the electronic element 23.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571)270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
Prosecution Insights