DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/15/2023 was filed
and is in compliance with provision of 37 CFR 1.97. Accordingly, the information
disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
Specifically, the multilayer stack 52 is not shown in FIG. 1 of the drawings filed on 10/20/2023. The multilayer stack 52 is shown in FIG. 1 of the drawings filed on 09/15/2023. Applicant’s assistance is required in making the drawings consistent so the multilayer stack 52 is shown in the most recent set of drawings. Also, see the specification [0012] for details which shows multilayer stack 52 should be present in FIG. 1.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following feature(s) must be shown or the feature(s) cancelled from the claim(s):
“the complete third fin structure”, as recited in claims 7-20 (only a partial third fin is shown in the figure);
“implanting a dopant into the insulation material between the first and second fin structures”, as recited in claim 10;
“wherein the portion of the dielectric wall separating the first and second S/D regions has a height substantially less than a height of the portion of the dielectric wall under the first and second gate electrode”, as recited in claim 18.
No new matter should be entered. It is also suggested that Applicant enhance the drawing to show the insulation material has been doped.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered, and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In [0042], line 5 “substrate 101” appears to be a typo. Changing to “substrate 50” is suggested to be consistent with referenced areas in the specification.
In [0047], line 1 “ILD layer 164” appears to be a typo. Changing to “(ILD) layer 86” is suggested to be consistent with referenced areas in the specification.
Appropriate correction is required.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 4, lines 1-2, recite “formed by atomic layer deposition”. It is suggested the limitation be changed to “formed by an atomic layer deposition process”, or a similar phrase, to be consistent with limitations recited in claims 5 and 6. Appropriate correction is required.
Dependent claims 5-6 are also objected to as they depend from claim 4.
Claim 18, lines 1-9, recite “forming a sacrificial gate structure over a portion of the first fin structure, a portion of the second fin structure, and a portion of the dielectric wall; recessing exposed portions of the first fin structure, exposed portions of the second fins structure, and exposed portions of the dielectric wall; forming first and second source/drain (S/D) regions from the recessed first and second fins, wherein the first S/D region is separated from the second S/D region by the dielectric wall; and forming an interlayer dielectric (ILD) layer over the first and second S/D regions”, in reference to figure 16 which is a top view of the claimed device. The examiner notes and brings to Applicant’s attention, if it is critical for this feature to only appear in a top view, the examiner suggests that the language in claim 18 be amended to reflect “in a top view”.
Dependent claims 19-20 are also objected to as they depend from claim 18.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 5-6, 15 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3, lines 2-3, recite the term “about” which is a relative term and renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Correction is required.
Claim 5, lines 1-2, recite “the first dielectric layer and the second dielectric layer are formed by a same process”. It is suggested the limitation be changed to “the first dielectric layer and the second dielectric layer are formed by the same atomic layer deposition process”, or a similar phrase, for definiteness and clarity and to be consistent with limitations recited in claim 4. Appropriate correction is required.
Claim 6, lines 1-2, recite “the first dielectric layer and the second dielectric layer are formed by different processes”. It is suggested the limitation be changed to “the first dielectric layer and the second dielectric layer are formed by a different process”, or a similar phrase, for definiteness and clarity and to be consistent with limitations recited in claim 4. Appropriate correction is required.
Claims 15 and 17 recite in at least lines 15 and 4, respectively, the term “substantially” which is a relative term and renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Correction is required.
Dependent claims 18-20 are also rejected to as they depend from claim 17.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kao (US 2021/0376113 Al) in view of Chen (US 2014/0246731 Al).
Regarding claim 1, Kao teaches in (FIGS. 2-7; [0005]) a method, comprising:
forming first (farthest left 204) and second fin structures (second from the right 204 in FIG. 2; [0014-0019]) over a substrate (202 in FIG. 2; [0014]);
forming a dielectric wall (208/2080 in FIG. 4-6; [0021]) between the first (farthest left 204) and second fin structures (second from right 204 in FIG. 6); [0014-0019]), comprising:
depositing a first dielectric layer (208 in FIG. 4; [0019]) between the first (farthest left 04) and second fin structures (second from the right 204 in FIG. 4; [0014-0019]), wherein a seam (209’ in FIG. 4; [0019]) is formed in the first dielectric layer (208);
performing a process to remove (Chemical Mechanical Planarization CMP in FIG. 5 [0020]) a portion of the first dielectric layer (208);
performing an isotropic etch process (FIG. 6; [0021]), wherein the seam (209) has a "V" shaped cross-sectional profile (209; FIG. 6); and
depositing a second dielectric layer (210 in FIG. 7; [0022]) between the first (farthest left 204) and second fin structures (second from the right 204 in FIG. 4; [0014-0019]), wherein the seam (209) is filled; and
forming shallow trench isolation regions (rightmost/leftmost 2060 in FIG. 6; [0021]) adjacent the first (farthest left 204) and second (second from the right) fin structures.
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FIG. 7 of Kao (Annotated): For the record, the inserted figure depicts first (farthest left 204), second (second from the right 204) and third (second from the left 204) fins structures.
Kao fails to disclose performing an anisotropic etch process to remove a portion of the first dielectric layer to expose the seam and performing the isotropic etch process to enlarge an opening of the seam. Kao does not explicitly state “to expose the seam” and “to enlarge an opening of the seam”.
However, Chen does teach a method in FIGS. 2-11 comprising: performing an anisotropic etch process (dry etching in FIG. 9A; [0020-0021]) to remove a portion (D”; [0023]) of the first dielectric layer (40; [0020]) to expose the seam (38 in FIG. 9B; [0021]); and also
performs the isotropic etch process (wet etching in FIG. 9B; [0023-0024]) to enlarge an opening (38; [0021]) of the seam (38; [0021]).
Kao and Chen are analogous art to the claimed invention because they are directed to a method of forming a semiconductor device with similar process steps involving forming dielectric walls/isolation between fin structures and forming shallow trench isolation regions, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kao in view of Chen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kao by performing an anisotropic etch process to remove a portion of the first dielectric layer to expose the seam, as taught by Chen ([ 0020-0021]; figure 7A-7B), thereby substituting the anisotropic etch in Chen for the chemical mechanical planarization (CMP) process in Kao, for the same purpose, with the motivation that an anisotropic etch is well known as a substitutional etch equivalent (MPEP 2144.06) for chemical mechanical planarization (CMP).
It would also have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kao by performing an isotropic etch process to enlarge an opening of the seam, as taught by Chen, with the motivation that using an isotropic etch to enlarge an opening of the seam increases the fill factor of the second dielectric layer, as taught by Chen ([0020-0021]).
Regarding claim 2, Kao in view of Chen discloses the method of claim 1 as explained above. In addition, Kao discloses wherein the first dielectric layer (208) and the second dielectric layer (210) comprise a same material (Each comprise silicon; Kao; [0019 and 0022]).
Regarding claim 3, as best understood, Kao in view of Chen, teaches the method of claim 2. Additionally, Kao teaches wherein the first dielectric layer (208; SiOCN; FIG.7; [0022]) and the second dielectric layer (210; SiCN; FIG. 7; [0022]) comprise SiCN,
Kao in view of Chen does not disclose the first dielectric layer has a thickness ranging from about 7 nm to about 9 nm, and the second dielectric layer has a thickness ranging from about 3 nm to about 4 nm.
However, Kao’s Fig. 7, appears to discuss the general relationship between the thicknesses of the first dielectric (208 in FIG.7; [0022]) and the second dielectric layer (210 in FIG. 7; [0022]). Kao appears to teach the thickness of the first dielectric layer (208) being larger than the thickness of the second dielectric layer (210) (Kao; [0022]). In as much as what is shown and described in Applicant’s disclosure for this feature and noting the specification does not appear to disclose criticality or unexpected results when describing the thickness ranges, it can be interpreted that the thickness ranges recited are related to an optimization of design choice and parameters.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kao wherein the first dielectric layer would have a thickness ranging from about 7 nm to about 9 nm, and the second dielectric layer would have a thickness ranging from about 3 nm to about 4 nm, with the motivation that Kao teaches the thickness range is required for the proper functioning and manufacturing of the device. The thickness of the first dielectric layer (208) needs to be larger than the thickness of the second dielectric layer (210) because it affects structural integrity (the seam issue). For example, Kao teaches if layer 210 is >20% of layer 208, the inclusion of too many oxygen atoms throughout the fin will reduce the etch selectivity needed for later manufacturing steps (Kao; [0022]).
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (In re Aller, 105 USPQ 233). In this case the relationship between the thicknesses of the first and second dielectric layers may be optimized for desired device performance.
Regarding claim 4, Kao in view of Chen discloses the method of claim 1 as explained above. Additionally, Kao discloses wherein the first dielectric layer (208 in FIG. 4; [0019]) is formed by atomic layer deposition (Kao; [0019]).
Regarding claim 6, as best understood, Kao in view of Chen discloses the method of claim 4 as explained above. In addition, Kao discloses wherein the first dielectric (208 in FIG. 4; [0019]) layer and the second (212 in FIG. 7; [0022]) dielectric layer are formed by different processes (Kao; [0022]).
Regarding claim 7, Kao in view of Chen discloses the method of claim 1 as explained above. In addition, Kao discloses further comprising forming a third fin (farthest right 204 in FIG. 2; [0014]) structure over the substrate (202 in FIG. 2; [0014]) prior to forming the dielectric wall (2080 in FIG. 6; Kao; [0021]).
Regarding claim 8, Kao in view of Chen discloses the method of claim 7 as explained above. In addition, Kao discloses wherein the first dielectric layer (208 in FIG. 4; [0019]) and the second dielectric layer (210 in FIG. 7; [0022]) are formed between the second (second from the right 204) and third (second from the left 204) fin structures (Kao; [0022]).
Regarding claim 9, Kao in view of Chen teaches the method of claim 8.
Additionally, Kao teaches further comprising removing the first dielectric layer (208) formed between the second (middle 3), and third fin (farthest right 3) structures prior to forming shallow trench isolation regions (rightmost/leftmost 2060 in FIG. 6; [0021]). Kao also teaches the second dielectric layer (210) is deposited by selective deposition.
However, Kao in view of Chen does not teach further comprising removing the second dielectric layer formed between the second (middle 3), and third fin (farthest right 3) structures prior to forming shallow trench isolation regions (rightmost/leftmost 2060 in FIG. 6; [0021]). There is no need to remove Kao’s second dielectric layer (210) deposited by selective deposition.
It would have been obvious to one of ordinary skills in the art, before the effective filing date of the claimed invention, to modify the selective deposition method of the second dielectric layer (210) of Kao, by replacing it with a conformal deposition method of the second dielectric layer and a subsequent step of removing the conformal second dielectric layer (210) to reveal the same conformal profile of the second dielectric layer (210) shown in FIG. 7. The claimed limitation is met therefore by substituting the selective deposition method in Kao for a conformal deposition method and removal process, for the same purpose, with the motivation that a conformal deposition method and removal process is well known as a substitutional equivalent (MPEP 2144.06).
Claim(s) 10-11 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kitamura (US 2008/0251883 Al) in view of Peng (US 2019/0385898 Al) and further in View of Cheng (US 20110111592 A1).
Regarding claim 10, Kitamura discloses (FIGS. 3A-12A) a method, comprising:
forming first (1st in Annotated FIG.9A), second (2nd in Annotated FIG.9A), and third (3rd in Annotated FIG.9A) fin structures over a substrate (1 in Annotated FIG.9A; [0047]);
depositing a dielectric layer (9; FIG. 6A; [0046]) between the first (1st) and second (2nd) fin structures and between the second (2nd) and third (3rd) fin structures, wherein a seam (9a; FIG. 6A; [0046] is formed in the dielectric layer (9) between the first (1st) and second (2nd) fin structures;
removing portions of the dielectric layer (9 in FIG. 7A; [0059]) between the first (1st) and second (2nd) fin structures to expose the seam (9a in FIG. 7A) and between the second (2nd) and third (3rd) fin structures to expose a layer underneath;
depositing an insulation material (10; FIG. 8A; [0047]) to embed the first (1st), second (2nd), and third (3rd) fin structures, wherein the insulation material (10) is in contact with the exposed layer underneath between the second (2nd) and third (3rd) fin structures and the seam (9a) between the first (1st) and second (2nd) fin structures is filled with the insulation material (10);
performing a process (CMP in FIG. 9A; [0059]), wherein the insulation material (10) between the first (1st) and second (2nd) fin structures is removed ([0059]).
Kitamura fails to disclose depositing a liner layer around the first, second, and third fin structures; removing portions of the dielectric layer between the second and third fin structures to expose the liner layer; depositing an insulation material, wherein the insulation material is in contact with the liner layer between the second, and third fin structures, implanting a dopant into the insulation material between the first and second fin structures; and performing an etch process, wherein the insulation material between the first and second fin structures is etched at a slower rate than the insulation material between the second and third fin structures (Kitamura only teaches a CMP process is performed rather than an etch process).
However, Peng teaches (FIGS. 1-8; [0004]) a method comprising: depositing a liner layer (24 in FIG. 2; [0019]) around the first (fourth from the left 22 in FIG. 2; [0017]), second (fifth from the left 22 in FIG 2; [0017]), and third fin (farthest right 22 in FIG 2; [0017]) structures; removing portions of a dielectric layer (oxygenized dielectric material 26 which includes 24 is removed in FIG. 5A; [0028]) to expose the liner layer (24/26 in FIG. 5A; [0042]); and depositing an insulation material, wherein the insulation material (28 in FIG. 5A; [0040]) is in contact with the liner layer (24/26) between the second (fifth from the left 22), and third (farthest right 22) fin structures.
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FIG. 7A of Kitamura
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FIG. 9A of Kitamura (Annotated): For the record, the inserted figure depicts first (1st Fin), second (2nd Fin), and third (3rd Fin) fin structures where a liner layer is deposited around the first (1st Fin), second (2nd Fin), and third (3rd Fin) fin structures.
Further, Cheng teaches a method in FIGS. 1-8, comprising: implanting a dopant (ions 26 in FIG. 3A and 3B; [0033]) into an insulation material ( 24 in FIG. 3A and 3B; [0033]) between the first (leftmost 20) and second (middle 20) fin structures; and performing an etch process (e. g. wet or dry or reactive ion etching; [0034]), wherein the insulation material (24) between the first and second fin structures is etched at a slower rate than the insulation material (22 in FIG. 3A and 3B) between the second (middle 20) and third (rightmost 20) fin structures. The examiner notes that Cheng does not explicitly state that the insulation between the first and second fin structures is etched at a slower rate than the insulation material between the second and third fin structures. However, Cheng does teach that the implanted insulation material (24) would be etched at a slower rate than the unimplanted insulation material (22), where selective ion implantation occurs between fins (20). Implanting in selective portions of the insulation material (22) versus not implanting in other portions allows for defining which gaps between fins receive protective modification, enabling high-precision selective etching across the device array (Cheng; [0033]).
Kitamura, Peng and Cheng are analogous art to the claimed invention because they are directed to a method of forming a semiconductor device with similar process steps involving forming dielectric/isolation walls between fin structures and forming shallow trench isolation regions, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kitamura in view of Peng and Cheng because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kitamura by depositing a liner layer around the first, second, and third fin structures and by removing portions of the dielectric layer between the second and the third fin structures to expose the liner layer (See annotated FIG. 9A), and further depositing an insulation material, wherein the insulation material is in contact with the liner layer between the second, and third fin structures with the following motivation . Forming the liner layer would ensure the integrity of the underlying layer before subsequent removal or etching steps and removing the dielectric layer to expose the liner layer to prepare for subsequent device layers and to form low density multi material shallow trench isolation structures which have increased strength and structural integrity (Peng; [0027] [0034] [0035] and 0041])
It would have been further obvious to modify the method of Kitamura by implanting a dopant (ions 26 in FIG. 3A and 3B; [0033]) into an insulation material ( implanted spacers 22/undesirable portions 24 in FIG. 3A and 3B; [0033]) between the first (leftmost 20) and second (middle 20) fin structures and performing an etch process (e. g. wet or dry or reactive ion etching; [0034]), wherein the insulation material between the first and second fin structures is etched at a slower rate than the insulation material ( un-implanted spacers 22 in FIG. 3A and 3B) between the second (middle 20) and third (rightmost 20) fin structures with the following motivation. Selective ion implantation permits choosing where to remove material across the device, allowing for high-precision selective etching across the device. Using the etch process (i.e., wet, dry, or reactive ion etch) of Cheng instead of Kitamura's CMP process [0059] is a well-known substitutional equivalent (MPEP 2144.06) to achieve desired insulation material shapes (Cheng; [0002], [0033], and [0034]). It's obvious that using selective ion implantation permits precise selection of which gaps between fins receive ions,
Regarding claim 11, Kitamura in view of Peng and Cheng disclose the method of claim 10 as explained above. In addition, Kitamura discloses wherein the dielectric layer (9) and the insulation material (10 in FIG. 9A; [0046]) comprise different materials (HDP SiO film 9 and polysilazane 10; [0007] and [0046]).
Regarding claim 13, Kitamura in view of Peng and Cheng disclose the method of claim 10 as explained above.
Kitamura in view of Peng and Cheng as applied to claim 10 above, do not disclose, wherein the liner layer comprises a semiconductor material.
However, Peng further teaches wherein the liner layer (24 in FIG. 2; [0019]) comprises a semiconductor material (Si; [0027]).
Kitamura, Peng and Cheng are analogous art to the claimed invention because they are directed to a method of forming a semiconductor device with similar process steps involving forming dielectric/isolation walls between fin structures and forming shallow trench isolation regions, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kitamura in view of Peng and Cheng because they are from the same field of endeavor.
It would been obvious to one of ordinary skill in the art, before the effective filing
date of the claimed invention, to further modify Kitamura in view of Peng to include the liner layer comprised of a semiconductor material (Si; [0027]), as taught by Peng, since the liner layer being made of a semiconductor material comprising low density (porous) material can permit efficient penetration of species to convert the dielectric material into another dielectric material (Peng; [0027] and [0034]).
Regarding claim 14, Kitamura in view of Peng and Cheng disclose the method of claim 10 as explained above.
Kitamura in view of Peng and Cheng as applied to claim 10 above, do not disclose, wherein the dielectric layer is deposited by atomic layer deposition, and the insulation material is deposited by flowable chemical vapor deposition.
However, Peng further teaches wherein the dielectric layer (24 in FIG. 2.; [0019]) is deposited by atomic layer deposition, and the insulation material (28 in FIG. 4; [0038]) is deposited by flowable chemical vapor deposition.
Kitamura, Peng and Cheng are analogous art to the claimed invention because they are directed to a method of forming a semiconductor device with similar process steps involving forming dielectric/isolation walls between fin structures and forming shallow trench isolation regions, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kitamura in view of Peng and Cheng because they are from the same field of endeavor.
It would been obvious to one of ordinary skill in the art, before the effective filing
date of the claimed invention, to further modify Kitamura in view of Peng to include the dielectric layer deposited by atomic layer deposition, and the insulation material deposited by flowable chemical vapor deposition, as taught by Peng, since ALD provides the precision required for the conformal dielectric layers, while FCVD provides the "flowable" capability necessary to fill the enlarged "V" shaped seam without trapping air or creating new seams (Peng; [0019] and [0038]).
Regarding claim 15, as best understood, Kitamura in view of Peng and Cheng teach the method of claim 10, as explained above.
However, Kitamura in view of Peng and Cheng do not disclose, wherein a distance between the first and second fin structures is substantially smaller than a distance between the second and third fin structures.
However, Peng further teaches wherein a distance between the first (fourth from the left 22) and second (fifth from the left 22) fin structures is substantially smaller than a distance between the second (fifth from the left 22) and third (farthest right 22) fin structures (Annotated FIG. 1A below).
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FIG. 1A of Peng (Annotated): For the record, the inserted figure depicts first (fourth from the left 22), second (fifth from the left 22) and third (farthest right 22) fins where a first width W2 between the first (fourth from the left 22) and second first (fifth from the left 22) fins is substantially less than a second width W3 between the second (fifth from the left 22) and third first (farthest right 22) fins.
Kitamura, Peng and Cheng are analogous art to the claimed invention because they are directed to a method of forming a semiconductor device with similar process steps involving forming dielectric/isolation walls between fin structures and forming shallow trench isolation regions, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kitamura in view of Peng and Cheng because they are from the same field of endeavor.
It would been obvious to one of ordinary skill in the art, before the effective filing
date of the claimed invention, to further modify Kitamura in view of Peng whereby a distance between the first and second fin structures is substantially smaller than a distance between the second and third fin structures, as taught by Peng, since trenches can have various widths between neighboring fins, in any configuration or pattern, which in turn affects device density ([Peng; 0017]).
Claims 17-19, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 2019/0385898 Al) in view of Chen (US 2014/0246731 Al)
Regarding claim 17, Peng in view of Chen teaches (FIGS. 1-8; [0004]) a method, comprising: forming first (fourth from the left 22), second (fifth from the left 22), and third fin ( farthest right 22) structures over a substrate (20), wherein a first trench (Unlabeled trench at W2; FIG. 1A [0017]) having a first width (W2; [0017]) is formed between the first (fourth from the left 22) and second (fifth from the left 22) fin structures, and a second trench (Unlabeled trench at W3; FIG. 1A [0017]) having a second width (W3; See inserted figure below) substantially greater (Trench widths are variable [0017]) than the first width is formed between the second (fifth from the left 22) and third fin (farthest right 22) structures;
depositing a first dielectric layer (26 in FIGS. 2-3; [0028]) in the first (Unlabeled trench at W2) and second trenches (Unlabeled trench at W3), and the first dielectric layer (26) is a conformal layer [0028];
removing portions of the first dielectric layer (26 in FIG. 5A [0042]) in the first (Unlabeled trench at W2) and second trenches (Unlabeled trench at W3);
depositing a second dielectric layer (28 in FIG. 4; [0037]) in the first (Unlabeled trench at W2) and second (Unlabeled trench at W3) trenches, and a dielectric wall (layers 26 and 28 in FIG. 4; [0040]) comprising the first (26) and second (28) dielectric layers is formed in the first trench (Unlabeled trench at W2);
removing the first (26) and second dielectric layers (28) in the second trench (Unlabeled trench at W3) wherein a top surface (upper plane in FIG. 5A; [42]) of the dielectric wall (laminate of 26 and 28) is located below a level of a top surface (upper plane) of the first fin structure (fourth from the left 22); and
forming a shallow trench isolation region (laminate of 26 and 28 in FIG. 5A; [0042]) in the second trench (Unlabeled trench at W3).
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FIG. 1A of Peng (Annotated): For the record, the inserted figure depicts first, second and third fins where a first width W2 between the first and second fins is substantially less than a second width W3 between the second and third fins.
Peng fails to teach wherein a seam is formed in the first dielectric layer in the first trench; wherein the seam in the first trench is exposed; removing portions of the first dielectric layer, depositing a second dielectric layer, wherein the seam in the first trench is filled with the second dielectric layer.
However, Chen teaches a method in FIGS. 2-11, comprising: wherein a seam (38 in FIG. 5A; [0016]) is formed in a first dielectric layer (36 in FIG. 5A; [0015]) in a first trench (32 in FIG. 4 and 5A; [0014] and [0015]); removing portions of a first dielectric layer, wherein the seam (38) in the first trench (32) is exposed ([0021]); depositing a second dielectric layer, wherein the seam (38) in the first trench (32) is filled with the second dielectric layer (40 in FIG. 7A; [0021]).
Peng and Chen are analogous art to the claimed invention because they are directed to a method of forming a semiconductor device with similar process steps involving forming dielectric/isolation walls between fin structures and forming shallow trench isolation regions, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Peng in view of Chen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to modify the method of Peng in view of Chen whereby a seam is formed in the first dielectric layer in the first trench and wherein the seam in the first trench is exposed. Additionally, a seam in the first trench is filled with the second dielectric layer as disclosed by Chen, such that the voids formed in the STI region reduce the effective k-value of the entire STI region. Furthermore, the parasitic capacitance of the device maybe reduced. The performance of the resulting integrated circuits is thus improved (Chen; [0035]).
Regarding claim 18, Peng in view of Chen discloses the method of claim 17 as explained above. In addition, Peng further teaches comprising: forming a sacrificial gate structure (32 in FIG. 7A, [0044]) over a portion of the first fin structure (Left 22), a portion of the second (Right 22) fin structure, and a portion of the dielectric wall (layers 26 and 28); recessing (in between FIGS. 4-5 and between FIGS. 6-7A; [0042] and [0048]) exposed portions of the first (Left 22) fin structure, exposed portions of the second (Right 22) fin structure, and exposed portions of the dielectric wall (layers 26 and 28); forming first (Left 42 in FIG. 7A; [0049]) and second (Middle 42 in FIG. 7A; [0049]) source/drain (S/D) regions from the recessed first (Left 22) and second (Right 22) fins, wherein the first (Left 42) S/D region is separated from the second ( Middle 42) S/D region by the dielectric wall (layers 26 and 28 in FIG. 4; [0040]) converted to 30; [0057]) in FIG. 7A; [0044]); and forming an interlayer dielectric (ILD) layer (52 in FIG. 7A; [0052]) over the first (Left 42) and second (Middle 42) S/D regions.
Regarding claim 19, Peng in view of Chen discloses the method of claim 18 as explained above. In addition, Peng further teaches comprising: removing the sacrificial gate structure (32 in FIG. 8A) and forming a first gate electrode layer (62 in FIG. 8A; [0055]) over the portion of the first (Left 22) fin structure and a second (66 in FIG. 8A; 0054]) gate electrode layer over the portion of the second (Right 22) fin structure, wherein the portion of the dielectric wall ( layers 26 and 28 in FIG. 4; [0040]) converted to 60 in FIG. 8A; [0057]) is under the first (62) and second (66) gate electrode layers.
Claim 5, as best understood, is rejected under 35 U.S.C. 103 as being unpatentable over Kao (US 2021/0376113 Al) and Chen (US 2014/0246731 Al) as applied to claim 4 above, and further in view of Ching (US 20200091142 A1).
Regarding claim 5, Kao in view of Chen and Ching discloses the method of claim 4 as explained above.
However, Kao in view of Chen and Ching does not explicitly disclose wherein the first dielectric layer and the second dielectric layer are formed by a same process.
Ching further teaches a first (130 in FIG. 12B; [0028]) dielectric layer and a second dielectric layer (142 in FIG. 12B; [0030]) are formed by a same process (CVD, plasma enhanced CVD, sputter, and other methods known in the art ([0028] and [0030])).
Kao, Chen and Ching are analogous art to the claimed invention because they are directed to a method of forming a semiconductor device with similar process steps involving forming dielectric/isolation walls between fin structures and forming shallow trench isolation regions, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kao in view of Chen and further in view of Ching because they are from the same field of endeavor.
It would been obvious to one of ordinary skill in the art, before the effective filing
date of the claimed invention, to modify Kao in view of Chen, and further in view of Ching to include the first dielectric layer and the second dielectric layer formed by a same process, as taught by Ching, which would minimize the types of processes and apparatus required for device fabrication.
Claims 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kitamura (US 2008/0251883 Al) in view of Peng (US 2019/0385898 Al) and Cheng (US 20110111592 A1) as applied to claim 10 above, and further in view of Kao (US 20210376113 A1).
Regarding claim 12, Kitamura in view of Peng further in view of Cheng disclose the method of claim 11 as explained above.
Kitamura in view of Peng further in view of Cheng does not disclose wherein the dielectric layer comprises SiN, SiC, SiCN, AlOx, or SiOCN, and the insulation material comprises silicon oxide.
However, Kao teaches wherein the dielectric layer (208; SiOCN; FIG.7; [0022]) comprises SiN, SiC, SiCN, AlOx, or SiOCN, and the insulation material (210; SiCN; FIG. 7; [0022]) comprises silicon oxide.
Kitamura, Peng, Cheng and Kao are analogous art to the claimed invention because they are directed to a method of forming a semiconductor device with similar process steps involving forming dielectric/isolation walls between fin structures and forming shallow trench isolation regions, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kitamura in view of Peng, Cheng and Kao because they are from the same field of endeavor.
It would been obvious to one of ordinary skill in the art, before the effective filing
date of the claimed invention, to further modify Kitamura in view of Kao wherein the dielectric layer comprises SiN, SiC, SiCN, AlOx, or SiOCN, and the insulation material comprises silicon oxide with the motivation that these materials are well known alternatives to the layers taught in Kitamura for semiconductor devices.
Regarding claim 16, Kitamura in view of Peng and Cheng disclose the method of claim 10 as explained above.
Kitamura in view of Peng and Cheng does not disclose wherein each of the first, second, and third fin structures comprises alternating first and second nanostructures.
However, Kao teaches wherein each of the first (farthest left 204 in FIG. 2), second (second from the right 204 in FIG. 2) and third (second from the left 204 in FIG. 2) fin structures comprises alternating first and second nanostructures (Si/SiGe nanostructures (not shown, [0011], [0016] and [0031]).
Kitamura, Peng, Cheng and Kao are analogous art to the claimed invention because they are directed to a method of forming a semiconductor device with similar process steps involving forming dielectric/isolation walls between fin structures and forming shallow trench isolation regions, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kitamura in view of Peng, Cheng and Kao because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing
date of the claimed invention, to further modify Kitamura in view of Kao to include wherein each of the first, second, and third fin structures comprises alternating first and second nanostructures, since the alternating Si/SiGe nanostructures of Kao can be used to form MBC transistors wherein the channel region of an MBC transistor may be formed from nanowires, nanosheets, or other nanostructures. An MBC transistor may also be referred to as a nanowire transistor or a nanosheet transistor (Kao; [0011], [0016] and [0031]).
Claim 20, as best understood, is rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 20190385898 A1) and Chen (US 2014/0246731 Al) as applied to claim 17 above, and further in view of Ching (US 20200091142 A1).
Regarding claim 20, Peng in view of Chen and further in view of Ching discloses the method of claim 18 as explained above.
However, Peng in view of Chen and further in view of Ching does not disclose wherein the portion of the dielectric wall separating the first and second S/D regions has a height substantially less than a height of the portion of the dielectric wall under the first and second gate electrode.
However, Ching teaches wherein the portion (130b) of the dielectric wall (142a, 140 and 130b) in FIG. 12B; [0041 and [0044]) separating the first (farthest right 200b in FIG. 12B;[ 0041]) and second (middle 200b in FIG.12B;[0041]) S/D regions has a height substantially less than a height of the portion (142a in FIG. 12B;[0030]) of the dielectric wall (142a, 140 and 130b in FIG. 12B; [0041) under the first (170 in FIG. 12B) and second (170 in FIG. 12B) gate electrode.
Peng, Chen and Ching are analogous art to the claimed invention because they are directed to a method of forming a semiconductor device with similar process steps involving forming dielectric/isolation walls between fin structures and forming shallow trench isolation regions, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Peng in view of Chen and Ching because they are from the same field of endeavor.
It would been obvious to one of ordinary skill in the art, before the effective filing
date of the claimed invention, to further modify Peng in view of Chen with Ching, disclose wherein the portion of the dielectric wall separating the first and second S/D regions has a height substantially less than a height of the portion of the dielectric wall under the first and second gate electrode, as taught by Ching, to provide a specific portion of the dielectric wall for avoiding source/drain epitaxy bridging between adjacent source/drain features (Ching; [0044]).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang et al. (US 20210313448 A1) and Frougier et al. (US 20200152734 A1) are cited to teach to a method of forming a semiconductor device with similar process steps involving forming dielectric/isolation walls between fin structures and forming shallow trench isolation regions, relevant to claims 1-20.
Conclusion
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/L.R.W./Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811