DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species (B, C and D), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5 February 2026.
Applicant’s election without traverse of Species A in the reply filed on 5 February 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 18 September 2023 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Hung-Chung Chien et al. (US 2022/0102274 A1; hereinafter “Chien”) in view of An-Chun Tu et al. (US 6309957 B1; hereinafter “Tu”).
Regarding Claim 1, Chien discloses a method for manufacturing a semiconductor device, the method comprising:
providing a buffer substrate (204 and 206, Fig. 2B, para [0018] describes a base semiconductor layer and a buried insulating layer forming a substrate);
forming a sacrificial contact film on the buffer substrate (210, Fig. 3B, para [0019] describes forming a sacrificial contact feature 210 on the buffer substrate);
forming a first base layer on the buffer substrate, the first base layer surrounding the sacrificial contact pattern (208, Fig. 3B, para [0018] describes forming an overlaying semiconductor layer 208 which can be seen surrounding the sacrificial contact pattern 210 in Fig. 3A);
forming an active pattern on the first base layer and the sacrificial contact pattern (212, Fig. 4B, para [0020] describes forming an epitaxial stack 212 over the first base layer 208 and sacrificial contact pattern 210), the active pattern extending in a first direction parallel to an upper surface of the first base layer (Fig. 4C depicts the active pattern 212 extending in a first X direction parallel to an upper surface of the first base layer 208);
forming a gate electrode on the active pattern (230, Fig 7A, para [0027] describes forming a gate electrode layer 230 on the active pattern 212), the gate electrode extending in a second direction intersecting the first direction and parallel to the upper surface of the first base layer (Fig. 7A depicts the gate electrode layer 230 extending in a second Y direction parallel to an upper surface of the first base layer 208);
forming a source/drain pattern on a side surface of the gate electrode (244, Fig. 13C, para [0035] describes forming S/D epitaxial features which can be seen on a side surface of gate electrodes in Fig. 14C), the source/drain pattern is directly connected to the active pattern (244, Fig. 13C depicts wherein the source/drain pattern 244 is directly connected to layer 216 of the active pattern 212), wherein the source/drain pattern overlaps the sacrificial contact pattern in a third direction intersecting the first direction and the second direction and perpendicular to the upper surface of the first base layer (244, Fig. 13C depicts wherein the source/drain pattern overlaps the first contact pattern 210 in a third Z direction intersecting the first X direction and the second Y direction and perpendicular to the upper surface of the first base layer 208);
exposing the sacrificial contact pattern by removing the buffer substrate (204 and 206, Fig. 18C and Fig. 19C, para [0041] describes thinning down the backside of the device by removing the base semiconductor layer 204 of the buffer substrate and para [0042] describes removing the buried oxide layer 206 of the base substrate until the sacrificial contact pattern 210 is exposed); and
forming a lower source/drain contact directly connected to the source/drain pattern by replacing the exposed sacrificial contact pattern (282, Fig. 20C and Fig. 21C, para [0044] describes forming a backside conductive contact via 282 in the trench 280 that is formed by removal of the sacrificial contact pattern 210 wherein the lower source/drain contact 282 is directly connected to the source/drain pattern 244).
Chien fails to explicitly disclose forming a sacrificial contact pattern by patterning the sacrificial contact film.
However, It would have been obvious to one of ordinary skill in the art at the time the invention was made to form a sacrificial contact pattern by patterning the contact film instead of forming a sacrificial contact pattern by depositing a sacrificial contact film in the trench formed through patterning the first base layer since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
Furthermore, Tu teaches a similar method for manufacturing a semiconductor device comprising providing a buffer substrate (10, 12 and 14, Fig. 1A, column 5, lines 50-56 describe a semiconductor substrate 10 with insulating layers 12 and 14);
forming a sacrificial contact film on the buffer substrate (18, Fig. 1A, column 5, lines 56-62 describe forming a sacrificial blanket layer 18 on the substrate 10, 12 and 14);
forming a sacrificial contact pattern by patterning the sacrificial contact film (18, Fig. 1A, column 5, lines 56-62 describe patterning and etching the blanket sacrificial contact film to form polysilicon islands 18);
forming a first base layer on the buffer substrate, the first base layer surrounding the sacrificial contact pattern (20, Fig. 1B, column 5, lines 65-67 and column 6, lines 1-3 describe depositing a dielectric material 20 around the sacrificial contact patterns 18);
The primary reference, Chien, only requires etch selectivity between the two materials of the sacrificial contact pattern and the first base layer, wherein Chien discloses the first base layer and sacrificial contact pattern may be comprises of a dielectric material, to create a sacrificial structure, wherein Tu discloses performing such a process through a different process order such as shown. The combination of Chien and Tu does not bodily incorporate the copper and dielectric structures of Tu and is used to teach the process order of depositing sacrificial material, patterning the sacrificial material to a required shape, and then depositing a base layer surrounding the sacrificial material to apply a known technique to a known method ready for improvement to yield predictable results.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chien with Tu to disclose a method for manufacturing a semiconductor device comprising forming a sacrificial contact pattern by patterning a sacrificial contact film to apply a known technique to a known method ready for improvement to yield the predictable result of providing a sacrificial contact pattern in a backside layer of a device at a position where a source/drain contact may replace the sacrificial contact pattern (see MPEP 2143 (I)(D)).
Regarding Claim 8, the combination of Chien and Tu discloses the method of claim 1, further comprising:
the first base layer includes a first surface (Chien, FF, annotated Fig. 4B depicts a first surface FF of the first base layer 208) and a second surface opposite to each other in the third direction (Chien, SF, annotated Fig. 4B depicts a second surface SF of the first base layer 208 opposite of the first surface FF in a third Z direction);
forming a backside wiring pattern on the first surface of the first base layer (Chien, 284, Fig. 22C, para [0045] describes backside interconnect layers 284 formed on the first surface FF of the first base layer 209), the backside wiring pattern is directly connected to the lower source/drain contact (Chien, 284, Fig. 22C, para [0045] describes forming backside interconnect layers 284 with backside power rails electrically connected to the lower source/drain contact 282 and is shown in direct contact in Fig. 22C),
and
the active pattern is disposed on the second surface of the first base layer (Chien, 212, annotated Fig. 4B depicts active pattern 212 being disposed on the second surface SF of the first base layer 208).
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Regarding Claim 9, the combination of Chien and Tu discloses the method of claim 1, wherein:
the active pattern includes a plurality of channel patterns spaced apart from each other in the third direction (216, Fig. 6C, para [0020] describes wherein active pattern 212 includes a plurality of epitaxial layers 216 forming channel layers spaced apart from each other in the third Z direction by epitaxial layers 214); and
each of the plurality of channel patterns extends in the first direction to penetrate the gate electrode (220, Fig. 7A, para [0024] describes fins 220 of the active patterns 212 comprising channel patterns 216 extending in the first X direction to penetrate the gate electrode layer 230).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Hung-Chung Chien et al. (US 2022/0102274 A1; hereinafter “Chien”) in view of An-Chun Tu et al. (US 6309957 B1; hereinafter “Tu”) and in further view of Kuo-Cheng Chiang et al. (US 2021/0134721 A1; hereinafter “Chiang”).
Regarding Claim 2, the combination of Chien and Tu disclose all the limitations of claim 1.
Chien and Tu fail to explicitly disclose the method of claim 1, wherein the forming of the sacrificial contact film includes performing an epitaxial growth process using the buffer substrate as a seed layer.
However, Chiang teaches a similar method for manufacturing a semiconductor device, wherein the forming of the sacrificial contact film includes performing an epitaxial growth process using the buffer substrate as a seed layer (240 and 242, Fig. 2, para [0017] describes epitaxially growing a silicon germanium layer 240 used as a sacrificial contact film over the lightly doped p-type region 242 of the substrate 50 wherein para [0015] describes the semiconductor substrate may include silicon such that a resulting substrate layer 242 would be comprised of silicon and be used as a seed layer to epitaxially grow sacrificial contact film 240).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chien and Tu with Chiang to perform a simple substitution of one known element, such as the silicon based dielectric layer used to form the dummy contact pattern as disclosed in Chien for another, such as the sacrificial silicon germanium layer of Chiang to obtain predictable results when performing an epitaxial growth process on a silicon substrate and to disclose a method for manufacturing a semiconductor device wherein the forming of a sacrificial contact film includes performing an epitaxial growth process using a buffer substrate as a seed layer in order to provide the well-known advantage of providing a sacrificial layer that may be epitaxially grown on a substrate layer comprising different etch selectivity for subsequent processing steps.
Regarding Claim 3, the combination of Chien, Tu and Chiang disclose the method of claim 2, wherein:
the buffer substrate includes a silicon (Si) layer (Chiang, 242, Fig. 2, para [0015] describes wherein the substrate 50 comprising substrate layer 242 may be comprised of silicon further wherein Chien teaches a semiconductor layer 204 of the substrate 202 may include silicon); and
the sacrificial contact film includes a silicon germanium (SiGe) layer (Chiang, 240, Fig. 2, para [0017] describes wherein the sacrificial contact film 240 may comprise silicon-germanium further wherein Chiang teaches sacrificial contact feature 210 may include a silicon derivative material, such as silicon germanium).
Allowable Subject Matter
Claims 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 4, the claim is indicated as being allowable if rewritten in independent form because the prior art of record, Hung-Chung Chien et al. (US 2022/0102274 A1; hereinafter “Chien”), discloses the method of claim 1, wherein the forming of the first base layer () includes:
forming a second base layer surrounding the sacrificial contact pattern (208, Fig. 3B, para [0018] describes forming an overlying semiconductor layer 208 which can be seen surrounding sacrificial contact pattern 210 in Fig. 3B); and
replacing the second base layer with the first base layer after exposing the sacrificial contact pattern by removing the buffer substrate (286, Fig. 23C, para [0046] describes replacing the second base layer 208 with a first base dielectric layer 286 after exposing the sacrificial contact pattern 210 by removing the buffer substrate 204 and 206).
Allowable subject matter has been indicated because the prior art of record, either alone or in combination fails to teach or fairly suggest the features, “forming a second base layer surrounding the sacrificial contact pattern by performing an epitaxial growth process using the buffer substrate and the sacrificial contact pattern as a seed layer”.
Claims 5-7 are indicated as being allowable if rewritten in independent form due to their dependence on claim 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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