DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species A with claims 1-14 readable thereon in the reply filed on 5 February 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Examiner notices claim 14 appears to be directed to at least Species B, C and D. Therefore, Examiner has withdrawn claim 14 from consideration for examination. Applicant states in the remarks submitted on 5 February 2026 that Species A is elected for examination and is being treated as an election without traverse as indicated above and therefore claims 15-20 stand withdrawn as being drawn to non-elected species (B, C and D). Currently, the Examiner believes claim 14 is also drawn towards unelected species (B, C and D) as it requires a cover dielectric layer to be in contact with a top surface of a peripheral gate capping layer, as shown in at least Fig. 9A, Fig. 10A and Fig. 11A from which non-elected Species B, C and D is drawn.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 18 September 2023 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the dummy line capping layer" in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation “the dummy line capping layer” will be interpreted as “a dummy line capping layer”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5, 7-8 and 10-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Daeik Kim et al. (US 2017/0323893 A1; hereinafter “Kim”).
Regarding Claim 1, Kim teaches a semiconductor device, comprising:
a substrate (100, Fig. 17A, para [0031] describes a substrate) that includes a cell region (CAR, Fig. 2A and Fig. 17A, para [0031] describes a cell region CAR of a substrate 100) and a peripheral region (COR, Fig. 2A and Fig. 17A, para [0031] describes a core region COR wherein the core region COR is peripheral to the cell region CAR), wherein the cell region includes a cell active pattern (Fig. 17B, para [0036] describes a first dopant region SD1 and second dopant region SD2 comprised in a cell active pattern AC1 as shown in Fig. 2A wherein Fig. 17A and Fig. 17B are cross sectional views of Fig. 2A);
a cell gate structure on the cell active pattern (WL, Fig. 17A, para [0034] describes word lines WL that may intersect the cell active pattern AC1 in the cell region CAR);
a bit-line structure electrically connected to the cell active pattern (215 and 132, Fig. 17B, para [0038] describes connection contacts 215 of a bit-line structure connected to first dopant regions SD1 of the cell active pattern AR1 and para [0048] describes cell lower contacts 132 which may also be connected to the cell active patterns AR1 through SD2);
a peripheral gate structure on the peripheral region (CG, Fig. 17A, para [0046] describes a core gate structure CG in the peripheral core region COR);
a peripheral etch stop layer on the peripheral gate structure (251, Fig. 17A, para [0071] describes a portion of a buffer pattern 251 which may be used as an etch stop layer is formed on the peripheral gate structure CG); and
a cover dielectric layer on the peripheral etch stop layer (272, Fig. 17A, para [0039] describes a second insulating pattern 272 that may extend onto the core region COR and on the peripheral etch stop layer 251),
wherein the bit-line structure (CL, Fig. 2A and Fig. 17B describes cell conductive lines CL which are bit-line structures) includes:
a bit-line conductive layer (244, Fig. 17B, para [0037] describes sub-conductive line 244);
a bit-line dielectric layer on the bit-line conductive layer (224, Fig. 17B, para [0039] describes a first insulating pattern 224 on the bit-line conductive layer 244);
a cell etch stop layer on the bit-line dielectric layer (251, Fig. 17B, para [0093] describes a buffer pattern 251 on the bit-line dielectric layer 224 wherein para [0071] describes the buffer pattern 251 may be used as an etch stop layer); and
a bit-line capping layer on the cell etch stop layer (272_A, Fig. 17B, para [0043] describes a second insulating pattern 272 comprising a first portion 272_A on the cell etch stop layer 251 wherein the second insulating layer 272 is a capping layer of the bit line structure CL),
wherein the peripheral gate structure (CG, Fig. 17A) includes:
a peripheral gate conductive layer (243, Fig. 17A, para [0046] describes a gate electrode 243); and
a peripheral gate capping layer on the peripheral gate conductive layer (223, Fig. 17A, para [0067] describes a core mask pattern 223 on the peripheral gate conductive layer 243 and capping the peripheral gate structure CG).
Regarding Claim 3, Kim teaches the semiconductor device of claim 1, wherein
the peripheral gate structure further includes a gate sidewall capping structure (SP2, Fig. 17A, para [0047] describes a second spacer SP2 capping a sidewall of the peripheral gate structure CG) in contact with a sidewall of the peripheral gate capping layer (SP2 and 223, Fig. 17A depicts wherein the gate sidewall capping structure SP2 is in contact with a sidewall of the peripheral gate capping layer 223), and
the gate sidewall capping structure is between the sidewall of the peripheral gate capping layer and the peripheral etch stop layer (SP2, 223 and 251, Fig. 17A depicts wherein the gate sidewall capping structure SP2 is between the sidewall of the peripheral gate capping layer 223 and the peripheral etch stop layer 251).
Regarding Claim 5, Kim teaches the semiconductor device of claim 1, wherein
the substrate further includes a dummy region between the cell region and the peripheral region (BR, Fig. 17A, para [0039] describes a boundary region BR between the cell region CAR and the peripheral region COR wherein the boundary region BR comprises a dummy line structure DL),
the semiconductor device further comprises a dummy line structure that overlaps the dummy region (DL, Fig. 17A and Fig. 17B, para [0039] describes a dummy line structure DL that overlaps the dummy region BR), and
the peripheral etch stop layer covers the dummy line structure (251, Fig. 17A and Fig. 17B, para [0041] describes wherein the dummy line structure DL may comprise a portion of the peripheral etch stop layer 251 wherein the peripheral etch stop layer covers at least a portion of lower, side and upper surfaces of the dummy line DL).
Regarding Claim 7, Kim teaches the semiconductor device of claim 5, wherein
the dummy line structure further includes a dummy line sidewall capping structure (DS, Fig. 17B, para [0082] describes dummy spacers DS formed on sidewalls of the dummy lines DL) in contact with a sidewall of a dummy line capping layer (DS and 272_A, Fig. 17B, para [0043] describes a portion of the capping pattern 272 may correspond to a portion of the dummy line DL as shown by 272_A in a C-C’ view as shown in Fig. 17B wherein dummy spacers DS are formed on a lower portion of the sidewall of the dummy line capping layer 272_A), and
the dummy line sidewall capping structure is between the sidewall of the dummy line capping layer and the peripheral etch stop layer (DS, 272_A and 251, Fig. 17B depicts wherein the dummy line sidewall capping structure is between the dummy line capping layer 272_A and peripheral etch stop layer 251 as shown in the C-C view).
Regarding Claim 8, Kim teaches the semiconductor device of claim 1, wherein
the peripheral etch stop layer includes a contact surface in contact with a bottom surface of the cover dielectric layer (272 and 251, annotated Fig. 17A depicts wherein the peripheral etch stop layer 251 on an upper surface of the peripheral gate structure CG includes a contact surface CS in contact with a bottom surface of the cover dielectric layer 272), and
the contact surface of the peripheral etch stop layer is at a level the same as a level of a top surface of the cell etch stop layer (CS and CES, annotated Fig. 17A depicts wherein the contact surface CS is at a level the same as a level of a top surface of the cell etch stop layer 251 in the cell region CAR as depicted by a cell etch stop portion CES).
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Regarding Claim 10, Kim teaches a semiconductor device, comprising:
a substrate (100, Fig. 17A, para [0031] describes a substrate) that includes a cell region (CAR, Fig. 2A and Fig. 17A, para [0031] describes a cell region CAR of a substrate 100) and a peripheral region (COR, Fig. 2A and Fig. 17A, para [0031] describes a core region COR wherein the core region COR is peripheral to the cell region CAR), wherein the cell region includes a cell active pattern (Fig. 17B, para [0036] describes a first dopant region SD1 and second dopant region SD2 comprised in a cell active pattern AC1 as shown in Fig. 2A wherein Fig. 17A and Fig. 17B are cross sectional views of Fig. 2A);
a cell gate structure on the cell active pattern (WL, Fig. 17A, para [0034] describes word lines WL that may intersect the cell active pattern AC1 in the cell region CAR);
a bit-line structure electrically connected to the cell active pattern (215 and 132, Fig. 17B, para [0038] describes connection contacts 215 of a bit-line structure connected to first dopant regions SD1 of the cell active pattern AR1 and para [0048] describes cell lower contacts 132 which may also be connected to the cell active patterns AR1 through SD2);
a peripheral gate structure on the peripheral region (CG, Fig. 17A, para [0046] describes a core gate structure CG in the peripheral core region COR);
a peripheral etch stop layer on the peripheral gate structure (251, Fig. 17A, para [0071] describes a portion of a buffer pattern 251 which may be used as an etch stop layer is formed on the peripheral gate structure CG); and
a cover dielectric layer on the peripheral etch stop layer (272, Fig. 17A, para [0039] describes a second insulating pattern 272 that may extend onto the core region COR and on the peripheral etch stop layer 251),
wherein the bit-line structure (CL, Fig. 2A and Fig. 17B describes cell conductive lines CL which are bit-line structures) includes:
a bit-line conductive layer (244, Fig. 17B, para [0037] describes sub-conductive line 244);
a bit-line dielectric layer on the bit-line conductive layer (224, Fig. 17B, para [0039] describes a first insulating pattern 224 on the bit-line conductive layer 244);
a cell etch stop layer on the bit-line dielectric layer (251, Fig. 17B, para [0093] describes a buffer pattern 251 on the bit-line dielectric layer 224 wherein para [0071] describes the buffer pattern 251 may be used as an etch stop layer); and
a bit-line capping layer on the cell etch stop layer (272_A, Fig. 17B, para [0043] describes a second insulating pattern 272 comprising a first portion 272_A on the cell etch stop layer 251 wherein the second insulating layer 272 is a capping layer of the bit line structure CL),
wherein the peripheral gate structure (CG, Fig. 17A) includes:
a peripheral gate conductive layer (243, Fig. 17A, para [0046] describes a gate electrode 243);
a peripheral gate capping layer on the peripheral gate conductive layer (223, Fig. 17A, para [0067] describes a core mask pattern 223 on the peripheral gate conductive layer 243 and capping the peripheral gate structure CG); and
a gate sidewall capping structure (SP2, Fig. 17A, para [0047] describes a second spacer SP2 capping a sidewall of the peripheral gate structure CG) in contact with the peripheral etch stop layer and a sidewall of the peripheral gate conductive layer (SP2, 251 and 223, Fig. 17A depicts wherein the gate sidewall capping structure SP2 is in contact with the peripheral etch stop layer 251 and in contact with a sidewall of the peripheral gate capping layer 223),
wherein the gate sidewall capping structure includes nitride (SP2, Fig. 17A, para [0047] describes wherein the gate sidewall capping structure SP2 may include a silicon nitride layer).
Regarding Claim 11, Kim teaches the semiconductor device of claim 10, wherein the gate sidewall capping structure does not include oxide (SP2, Fig. 17A, para [0047] describes wherein the gate sidewall capping structure SP2 may include a silicon nitride layer wherein a silicon nitride layer would not include an oxide).
Regarding Claim 12, Kim teaches the semiconductor device of claim 10, further comprising a dielectric structure between the cell region and the peripheral region (111, Fig. 17A, para [0032] describes a device isolation layer 111 between the cell region CAR and peripheral region COR),
wherein the peripheral etch stop layer is in contact with a top surface of the dielectric structure (251 and 111, Fig. 17A depicts wherein the peripheral etch stop layer 251 extending from the peripheral region COR is in contact with a top surface of the dielectric structure 111).
Regarding Claim 13, Kim teaches the semiconductor device of claim 10,
wherein the peripheral etch stop layer is in contact with a top surface of the peripheral gate capping layer (251 and 223, Fig. 17A, para [0070] describes wherein the peripheral etch stop layer 251 is formed along a top surface of the peripheral gate capping layer 223).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Daeik Kim et al. (US 2017/0323893 A1; hereinafter “Kim”) in view of Yi-Hsiang Chao et al. (US 2023/0386822 A1; hereinafter “Chao”).
Regarding Claim 2, Kim disclose all the limitations of claim 1.
Kim fails to explicitly disclose the semiconductor device of claim 1, wherein the cell etch stop layer, the bit-line dielectric layer, and the bit-line capping layer include hydrogen, and a hydrogen concentration of the cell etch stop layer is different from a hydrogen concentration of the bit-line dielectric layer and a hydrogen concentration of the bit-line capping layer.
Kim does disclose in para [0041] wherein the cell etch stop layer (251) may include silicon nitride and in para [0039] wherein the bit-line dielectric layer (224) and bit-line capping layer (272) may include silicon oxynitride.
Chao further discloses a similar semiconductor device wherein the cell etch stop layer, the bit-line dielectric layer, and the bit-line capping layer include hydrogen (para [0154] describes forming a layer 410 that includes silicon nitride may be formed with a silicon nitride precursor including diiodosilane (SiH2I-2) and a reactant including methane (CH4) resulting in a silicon nitride material layer such as the cell etch stop layer 251 of Kim that would include hydrogen and wherein forming a silicon oxynitride layer such as the bit-line dielectric layer 224 and the bit-line capping layer 272 of Kim in a similar manner as forming the silicon nitride layer would further include hydrogen as well as oxygen as required to form a silicon oxynitride layer), and
a hydrogen concentration of the cell etch stop layer is different from a hydrogen concentration of the bit-line dielectric layer and a hydrogen concentration of the bit-line capping layer (para [0154] describes forming a silicon nitride layer including hydrogen and wherein upon forming a silicon oxynitride layer using a similar process would result in a silicon oxynitride layer comprising hydrogen wherein a resulting silicon nitride layer comprising hydrogen such as the cell etch stop layer 251 of Kim would have a different hydrogen concentration than the silicon oxynitride layers comprising hydrogen such as the bit-line dielectric layer 224 and the bit-line capping layer 272 of Kim and further wherein a hydrogen concentration present during a precursor gas and reactant forming process would result in different hydrogen concentrations due to imperfections present when forming a silicon nitride or silicon oxynitride with a precursor gas and reactant).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kim with Chao to further disclose a semiconductor device wherein a manufacturing process of forming a silicon nitride film and a silicon oxynitride film applies a known technique, such as using a precursor gas and reactant containing hydrogen to form silicon nitride and oxynitride resulting in a cell etch stop layer, bit-line dielectric layer and bit-line capping layer comprising hydrogen at different concentrations, to a known device such as a semiconductor device ready for improvement to yield predictable results (see MPEP 2143 (I)(D)).
Regarding Claim 9, Kim disclose all the limitations of claim 1.
Kim fails to explicitly disclose the semiconductor device of claim 1, wherein the peripheral gate capping layer, the peripheral etch stop layer, and the cover dielectric layer include carbon, and a carbon concentration of the peripheral etch stop layer is different from a carbon concentration of the peripheral gate capping layer and a carbon concentration of the cover dielectric layer.
Kim does disclose in para [0041] wherein the peripheral etch stop layer (251) may include silicon nitride and in para [0039] wherein the cover dielectric layer (272) may include silicon oxynitride and para [0046] describes wherein the peripheral gate capping layer (223) may correspond to the first insulating pattern (224) which may be a silicon oxynitride.
Chao further discloses a similar semiconductor device wherein the peripheral gate capping layer, the peripheral etch stop layer, and the cover dielectric layer include carbon (para [0154] describes forming a layer 410 that includes silicon nitride may be formed with a silicon nitride precursor including diiodosilane (SiH2I-2) and a reactant including methane (CH4) resulting in a silicon nitride material layer such as the peripheral etch stop layer 251 of Kim that would include carbon and wherein forming a silicon oxynitride layer such as the peripheral gate capping layer 223 and the cover dielectric layer 272 of Kim in a similar manner as forming the silicon nitride layer would further include carbon as well as oxygen as required to form a silicon oxynitride layer), and
a carbon concentration of the peripheral etch stop layer is different from a carbon concentration of the peripheral gate capping layer and a carbon concentration of the cover dielectric layer (para [0154] describes forming a silicon nitride layer including carbon and wherein upon forming a silicon oxynitride layer using a similar process would result in a silicon oxynitride layer comprising carbon wherein a resulting silicon nitride layer comprising carbon such as the peripheral etch stop layer 251 of Kim would have a different carbon concentration than the silicon oxynitride layers comprising carbon such as the peripheral gate capping layer 223 and the cover dielectric layer 272 of Kim and further wherein a carbon concentration present during a precursor gas and reactant forming process would result in different carbon concentrations due to imperfections present when forming a silicon nitride or silicon oxynitride with a precursor gas and reactant).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kim with Chao to further disclose a semiconductor device wherein a manufacturing process of forming a silicon nitride film and a silicon oxynitride film applies a known technique, such as using a precursor gas and reactant containing carbon to form silicon nitride and oxynitride resulting in a cell etch stop layer, bit-line dielectric layer and bit-line capping layer comprising carbon at different concentrations, to a known device such as a semiconductor device ready for improvement to yield predictable results (see MPEP 2143 (I)(D)).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Daeik Kim et al. (US 2017/0323893 A1; hereinafter “Kim”) in view of Hyejin Seong et al. (US 2021/0082924 A1; hereinafter “Seong”).
Regarding Claim 4, Kim discloses the semiconductor device of claim 3, further comprising a dielectric structure between the cell region and the peripheral region (111, Fig. 17A, para [0032] describes a device isolation layer 111 between the cell region CAR and peripheral region COR),
wherein an upper portion of the gate sidewall capping structure is in contact with the sidewall of the peripheral gate capping layer (SP2 and 223, Fig. 17A depicts wherein an upper portion of the gate sidewall capping structure SP2 is in contact with a sidewall of the peripheral gate capping layer 223), and
wherein a width of the upper portion of the gate sidewall capping structure is less than a width of the lower portion of the gate sidewall capping structure (SP2, Fig. 17A depicts wherein a width of the upper portion of the gate sidewall capping structure SP2 is less than a width of a lower portion of the gate sidewall capping structure SP2 contacting the substrate 100).
Kim fails to explicitly disclose wherein a lower portion of the gate sidewall capping structure is in contact with a top surface of the dielectric structure.
However, Seong teaches a similar semiconductor device, wherein a lower portion of the gate sidewall capping structure (150P, Fig. 10D, para [0088] describes a gate insulating spacer 150P capping a sidewall of a peripheral gate structure 140P) is in contact with a top surface of the dielectric structure (115 and 150P, Fig. 10D, para [0056] describes a region isolation film 150 separating a peripheral region PR form a cell region CR wherein a lower portion of the sidewall capping structure 150P is in contact with a top surface of the dielectric structure 115).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kim with Seong to further disclose a semiconductor device wherein a lower portion of the gate sidewall capping structure is in contact with a top surface of the dielectric structure in order to provide the well-known advantage of providing a contiguous dielectric region separating a peripheral region from a cell region so as to prevent possible parasitic current leakage between the two device regions which would result in undesirable effects in the semiconductor device.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Daeik Kim et al. (US 2017/0323893 A1; hereinafter “Kim”) in view of Hyejin Seong et al. (US 2021/0082924 A1; hereinafter “Seong”) and in further view of in view of Yi-Hsiang Chao et al. (US 2023/0386822 A1; hereinafter “Chao”).
Regarding Claim 6, Kim discloses the semiconductor device of claim 5, wherein
the dummy line structure (DL, Fig. 17A and Fig. 17B) includes a dummy line capping layer (272_A, Fig. 17B, para [0043] describes a portion of the capping pattern 272 may correspond to a portion of the dummy line DL as shown by 272_A in a C-C’ view as shown in Fig. 17B).
Kim fails to explicitly disclose wherein the dummy line structure includes a dummy line conductive layer and a dummy line capping layer on the dummy line conductive layer.
However, Seong teaches a similar semiconductor device wherein the dummy line structure (140D, Fig. 9A, para [0105] describes a dummy line structure 140D) includes a dummy line conductive layer (146, Fig. 9A, para [0077] describes a second metal conductive pattern 146 present in dummy line structure 140D as shown in Fig. 9A) and a dummy line capping layer on the dummy line conductive layer (148, Fig. 9A, para [0077] describes an insulating capping layer 148 covering the second metal conductive patterns 146 wherein the insulating capping layer 148 on the dummy line conductive layer 146 in the dummy line structure 140D would comprise a dummy line capping layer 148).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kim with Seong to further disclose a semiconductor device wherein a dummy line structure comprises a dummy line conductive layer and a dummy line capping layer on a dummy line conductive layer in order to provide the advantage of enabling a dummy line structure to be formed simultaneously with a bit line structure (Seong, para [0082]) resulting in the well-known advantage of simplifying a manufacturing process of a semiconductor device thereby decreasing manufacturing costs.
The combination of Kim and Seong fail to explicitly disclose wherein the dummy line capping layer and the peripheral etch stop layer include hydrogen, and a hydrogen concentration of the peripheral etch stop layer is different from a hydrogen concentration of the dummy line capping layer.
Kim does disclose in para [0041] wherein the peripheral etch stop layer (251) may include silicon nitride and in para [0039] wherein the dummy line capping layer (272_A) may include silicon oxynitride.
Chao further discloses a similar semiconductor device wherein the dummy line capping layer and the peripheral etch stop layer include hydrogen (para [0154] describes forming a layer 410 that includes silicon nitride may be formed with a silicon nitride precursor including diiodosilane (SiH2I-2) and a reactant including methane (CH4) resulting in a silicon nitride material layer such as the peripheral etch stop layer 251 of Kim that would include hydrogen and wherein forming a silicon oxynitride layer such as the dummy line capping layer 272_A of Kim in a similar manner as forming the silicon nitride layer would further include hydrogen as well as oxygen as required to form a silicon oxynitride layer), and
a hydrogen concentration of the peripheral etch stop layer is different from a hydrogen concentration of the dummy line capping layer (para [0154] describes forming a silicon nitride layer including hydrogen and wherein upon forming a silicon oxynitride layer using a similar process would result in a silicon oxynitride layer comprising hydrogen wherein a resulting silicon nitride layer comprising hydrogen such as the peripheral etch stop layer 251 of Kim would have a different hydrogen concentration than the silicon oxynitride layers comprising hydrogen such as the dummy line capping layer 272_A of Kim and further wherein a hydrogen concentration present during a precursor gas and reactant forming process would result in different hydrogen concentrations due to imperfections present when forming a silicon nitride or silicon oxynitride with a precursor gas and reactant).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kim and Seong with Chao to further disclose a semiconductor device wherein a manufacturing process of forming a silicon nitride film and a silicon oxynitride film applies a known technique, such as using a precursor gas and reactant containing hydrogen to form silicon nitride and oxynitride resulting in a peripheral etch stop layer and a dummy line capping layer comprise hydrogen at different concentrations, to a known device such as a semiconductor device ready for improvement to yield predictable results (see MPEP 2143 (I)(D)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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