DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/20/2025 is in compliance with the provisions on 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Amendments
Acknowledgment of receiving amendments to the claims, which were received by the Office on 11/10/2025.
Response to Arguments
Applicant's arguments filed 11/10/2025 have been fully considered but they are not persuasive.
In that remarks, applicant argues in substance:
Applicant argues: “Niwa, Kobayashi, and Shim, which are cited for showing an imaging device, do not remedy the failures of Ohkawa to describe or suggest the noted features of claim 1. In particular, since FIG. 11 of Niwa depicts a first wiring 22VSSa/b, a fourth wiring 22TRG-a/b, and a fifth wiring 22RST-a/b that are provided below a second wiring 23b and a third wiring 23a, Niwa is not sufficient to remedy the failure of Ohkawa. Additionally, since the Office Action fails to address where Kobayashi describes or suggest a fourth conductive layer configured to be the third wiring and a fifth conductive layer configured to be the second wiring, Kobayashi is not sufficient to remedy the failures of Ohkawa and Niwa. Furthermore, although Shim is cited for showing a capacitor electrode electrically connected to ground, Shim is not sufficient to remedy the failures of Ohkawa, Niwa, and Kobayashi.”
Examiner’s Response: Examiner respectfully disagrees. Claim language does not limit which orientation may be considered above or below with respect to the first, fourth and the fifth wirings and the second and third wirings. With reference to Ohkawa, Figure 2 may be considered to be top layer and Figure 4 may be considered to be a lower layer with Figure 3 being an intermediate layer between Figures 2 and 4. Therefore, Ohkawa is seen to disclose the fourth wiring, and the fifth wiring are provided over the second wiring and the third wiring. Niwa teaches the first wiring is in the same layer as the fourth wiring, and the fifth wiring. Therefore, the combination of Ohkawa and Niwa is seen to disclose “wherein the first wiring, the fourth wiring, and the fifth wiring are provided over the second wiring and the third wiring”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohkawa (US 2005/0237405 A1) in view of Niwa et al. (US 2017/0201702 A1) in view of Kobayashi et al. (US 2013/0264468 A1) in view of Shim (US 2008/0157152 A1).
Regarding claim 3, Ohkawa teaches a semiconductor device (Ohkawa, Figs. 1-4) comprising:
a photoelectric conversion element (Ohkawa, Figs. 1-4, photodiode PD1, Paragraph 0058);
a first transistor (Ohkawa, Figs. 1-4, transfer transistor TG1, Paragraph 0058);
a second transistor (Ohkawa, Figs. 1-4, source follower transistor SF-Tr, Paragraph 0059); and
a third transistor (Ohkawa, Figs. 1-4, reset transistor RST, Paragraph 0059);
wherein one of an anode and a cathode of the photoelectric conversion element is electrically connected to a ground (Ohkawa, Fig. 1, Paragraph 0049, The anode terminal of the photodiode PD is grounded.),
wherein the other of the anode and the cathode of the photoelectric conversion element is electrically connected to a gate of the second transistor via the first transistor (Ohkawa, Fig. 1, Paragraph 0049, The cathode of the photodiode PD1 is connected to the gate of transistor SF-Tr via transfer transistor TG1.),
wherein the gate of the second transistor is electrically connected to a second wiring (Ohkawa, Fig. 1, VR (Reset Voltage) Line, Fig. 4, VR line 36b, Paragraphs 0062 and 0093) via the third transistor (Ohkawa, Fig. 1, The gate of transistor SF-Tr is connected to VR line (second wiring) through reset transistor RST.),
wherein the second transistor is configured to output data to a third wiring (Ohkawa, Fig. 1, Signal Read Line, Fig. 4, signal read line 36a, Paragraphs 0056, 0062 and 0093),
wherein a second conductive layer configured to be a fourth wiring electrically connected to a gate of the first transistor (Ohkawa, Figs. 1 and 3, TG1 line 32b, Paragraphs 0061 and 0084), and a third conductive layer configured to be a fifth wiring electrically connected to a gate of the third transistor (Ohkawa, Figs. 1 and 3, RST Line 32c, Paragraphs 0063 and 0084) are provided so as to extend in a same direction in a same layer (Ohkawa, Fig. 3, Paragraph 0065),
wherein a fifth conductive layer (Ohkawa, Fig. 4, VR line 36b, Paragraph 0093) configured to be the second wiring (Ohkawa, Fig. 1, VR (Reset Voltage) Line, Fig. 4, VR line 36b) is provided in a same layer (Ohkawa, Fig. 4, Paragraph 0065) as a fourth conductive layer configured to be the third wiring (Ohkawa, Fig. 4, signal read line 36a, Paragraph 0093),
wherein, in the plan view, the second conductive layer intersects with the fourth conductive layer and the fifth conductive layer (Ohkawa, Figs 3-4, TG1 Line 32b (second conductive layer) intersects with signal read line 36a (fourth conductive layer) and VR line 36b (fifth conductive layer).),
wherein, in the plan view, the third conductive layer intersects with the fourth conductive layer and the fifth conductive layer (Ohkawa, Figs 3-4, RST Line 32c (third conductive layer) intersects with signal read line 36a (fourth conductive layer) and VR line 36b (fifth conductive layer).),
wherein, in the plan view, the fourth conductive layer overlaps with a channel formation region (Ohkawa, Fig. 2, gate electrode 24TG1, Paragraph 0076) of the first transistor (Ohkawa, Fig. 4, Signal read line 36a overlaps a portion of gate electrode 24TG1.), and
wherein the fourth wiring, and the fifth wiring are provided over the second wiring and the third wiring (Ohkawa, Figs. 2-3, Figure 2 is considered to be over Figure 3.).
However, Ohkawa does not teach a capacitor, wherein the anode of the photoelectric conversion element is electrically connected to a first wiring, wherein the cathode of the photoelectric conversion element is electrically connected to one electrode of the capacitor via the first transistor, wherein the other electrode of the capacitor is electrically connected to the first wiring; wherein a first conductive layer configured to be the first wiring, the second conductive layer, and the third conductive layer are provided so as to extend in a same direction in a same layer, wherein a sixth conductive layer is configured to be the gate of the second transistor and the one electrode of the capacitor, wherein, in a plan view, the first conductive layer intersects with the fourth conductive layer and the fifth conductive layer, wherein the first wiring is provided over the second wiring and the third wiring.
In reference to Niwa et al. (hereafter referred as Niwa), Niwa teaches a capacitor (Niwa, Fig. 2, FD 33a, Paragraph 0061, “The FD 33a is a floating diffusion area having a predetermined storage capacitor…”),
wherein an anode of the photoelectric conversion element is electrically connected to a first wiring (Niwa, Fig. 2, Paragraph 0059, The photoelectric conversion element is connected to ground., Fig. 11, horizontal signal line 22VSS-a/b, Paragraphs 0117-0119, The unlabeled contact on the left side of horizontal signal line 22VSS-a/b is used to ground PD 31a/b (see conclusion).),
wherein a cathode of a photoelectric conversion element is electrically connected to one electrode of the capacitor via a first transistor (Niwa, Fig. 2, transfer transistor 32a, Paragraph 0060)
wherein a first conductive layer configured to be the first wiring (Niwa, Fig. 11, horizontal signal line 22VSS-a/b), a second conductive layer (Niwa, Fig. 11, horizontal signal line 22TRG-a/b, Paragraph 0117), and a third conductive layer (Niwa, Fig. 11, horizontal signal line 22RST-a/b, Paragraph 0117) are provided so as to extend in a same direction (Niwa, Fig. 11, 22VSS, 22TRG and 22RST extend in the same direction.),
wherein, in a plan view, the first conductive layer (Niwa, Fig. 11, horizontal signal line 22VSS-a/b) intersects with a fourth conductive layer (Niwa, Fig. 11, vertical signal line 23a, Paragraph 0119),
wherein the first wiring, the fourth wiring, and the fifth wiring are provided over the third wiring (Niwa, Fig. 11, Lines 22VSS-a/b, 22TRG-a/b and 22RST-a/b are considered to be over vertical signal line 23a.).
These arts are analogous since they are both related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Ohkawa with the horizontal ground line (first conductive layer) as seen in Niwa since it is a known orientation of a ground line and would provide similar and expected results for grounding the photodiode. Further, by providing the first conductive layer configured to be the first wiring as a horizontal ground line, the limitation “wherein, in a plan view, the first conductive layer intersects with the fourth conductive layer and the fifth conductive layer” is met since the fourth conductive layer and the fifth conductive layer extend in the vertical direction. Further, by providing the first wiring in the same plane as the fourth and fifth wiring, the limitation “wherein the first wiring, the fourth wiring, and the fifth wiring are provided over the second wiring and the third wiring” is met.
However, the combination of Ohkawa and Niwa does not teach wherein the other electrode of the capacitor is electrically connected to the first wiring; wherein a first conductive layer, the second conductive layer, and the third conductive layer are provided in a same layer; and wherein a sixth conductive layer is configured to be the gate of the second transistor and the one electrode of the capacitor.
In reference to Kobayashi et al. (hereafter referred as Kobayashi), Kobayashi teaches wherein a first conductive layer (Kobayashi, Figs. 5 and 7, ground wire 15, Paragraph 0056-0057), the second conductive layer (Kobayashi, Figs. 5 and 7, control lines 11 or 12, Paragraph 0054, Control lines 11 and 12 are connected to the gates of the transfer transistors.), and the third conductive layer (Kobayashi, Figs. 5 and 7, reset line 26, Paragraph 0112) are provided in a same layer (Kobayashi, Fig. 7, Paragraph 0105).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Ohkawa and Niwa with the teaching of placing a horizontal ground line (as seen in Niwa) in the same layer as the signal lines for the gates transfer and reset transistors as seen in Kobayashi since it is a known layer for placing the conductive layers and would provide similar and expected results as placement for the three conductive lines.
However, the combination of Ohkawa, Niwa and Kobayashi does not teach wherein the other electrode of the capacitor is electrically connected to the first wiring; and wherein a sixth conductive layer is configured to be the gate of the second transistor and the one electrode of the capacitor.
In reference to Shim, Shim teaches a capacitor (Shim, Fig. 3 and 6, capacitor 170, capacitor electrode 175, capacitor electrode 171, Paragraphs 0025 and 0045),
wherein one of an anode and a cathode of a photoelectric conversion element (Shim, Figs. 3 and 6, photodiode 110) is electrically connected to one electrode of the capacitor (Shim, Figs. 3 and 6, capacitor electrode 171, Paragraph 0024 and 0027),
wherein the other electrode of the capacitor (Shim, Figs. 3 and 6, capacitor electrode 175) is electrically connected to ground (Shim, Figs. 3 and 6, ground signal GND, Paragraph 0031); and
wherein a sixth conductive layer is configured to be a gate of a second transistor and the one electrode of the capacitor (Shim, Fig. 6, Paragraphs 0027-0028 and 0045).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Ohkawa, Niwa and Kobayashi with the explicit teaching of grounding the capacitor and the teaching of forming an electrode of the capacitor with the same conductive layer as the gate of the second capacitor as seen in Shim to provide a reference potential for the capacitor and to avoid a need for a metal wiring to connect the drive transistor and the floating diffusion and may reduce the size of the unit pixel as well as increase the electron storing capacity of the floating diffusion node by minimizing the area for forming the capacitor (Shim, Paragraph 0027). Further, the limitation “wherein the other electrode of the capacitor is electrically connected to the first wiring” is met since the first wiring is ground.
Claims 1 and 2 are rejected for the same reasons as claim 3.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohkawa (US 2005/0237405 A1) in view of Niwa et al. (US 2017/0201702 A1) in view of Kobayashi et al. (US 2013/0264468 A1) in view of Shim (US 2008/0157152 A1) in view of Okita et al. (US 2006/0044434 A1).
Regarding claim 6, the combination of Ohkawa, Niwa, Kobayashi and Shim teaches the semiconductor device according to claim 3 (see claim 3 analysis). However, the combination of Ohkawa, Niwa, Kobayashi and Shim does not teach wherein a potential of the first wiring is supplied to a back gate of each of the first to third transistors.
In reference to Okita et al. (hereafter referred as Okita), Okita teaches wherein a potential of a first wiring is supplied to a back gate (Okita, Paragraph 0040, “A backgate potential of all the transistors and anode electrodes of the photodiodes are fixed to a constant potential, such as a ground potential, through the well contact 109.”) of each of a transfer transistor (Okita, Fig. 5, transfer MOS transistor 102a/b, Paragraph 0030) an amplifying transistor (Okita, Fig. 5, amplifying MOS transistor 106, Paragraph 0030), and a reset transistor (Okita, Fig. 5, reset MOS transistor 104, Paragraph 0030).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Ohkawa, Niwa, Kobayashi and Shim with the teaching of fixing the back gates of the transistors to the ground potential as seen in Okita since applying a back-bias voltage can raise the threshold voltage, giving more control over the transistor’s operation.
Claims 4 and 5 are rejected for the same reasons as claim 6.
Allowable Subject Matter
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
With regard to claim 7, prior art of record neither anticipates nor renders obvious:
“The semiconductor device according to claim 1, wherein the sixth conductive layer and the third conductive layer do not overlap with each other in the plan view.”
With regard to claim 8, prior art of record neither anticipates nor renders obvious:
“The semiconductor device according to claim 1, wherein the sixth conductive layer and the third conductive layer do not overlap with each other in the plan view.”
With regard to claim 9, prior art of record neither anticipates nor renders obvious:
“The semiconductor device according to claim 1, wherein the sixth conductive layer and the third conductive layer do not overlap with each other in the plan view.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Abe et al. (US 2005/0116251 A1): Abe et al. explicitly discloses a contact for grounding a photodiode to a wiring line (Abe, Fig. 3, metallic wire 56 and contact part 57, Paragraph 0059).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WESLEY JASON CHIU whose telephone number is (571)270-1312. The examiner can normally be reached Mon-Fri: 8am-4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Twyler Haskins can be reached at (571) 272-7406. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WESLEY J CHIU/ Examiner, Art Unit 2639
/TWYLER L HASKINS/ Supervisory Patent Examiner, Art Unit 2639