DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in the COUNTRY OF KOREA on 10/06/2022.
Election/Restrictions
Applicant's election without traverse of “Species A (claims 1-6 and 9-20)” in the reply filed on February 02, 2026, is acknowledged.
Claims 7-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6,9-12, and 16-20 are rejected under 35 U.S.C. 103 as being obvious over US 2016/0155723 A1; Lou; 06/2016; (“723”) in view of US 6,693,036 B1; Nogami et al.; 02/2004; (“036”).
Regarding Claim 1. 723 teaches in Figs. 6,10I and 14F about a semiconductor package comprising:
a first distribution structure (Fig. 6, item 608) including a plurality of first distribution patterns (Fig. 14F, at least items 1417 and 1418) disposed between a plurality of first lower surface connection pads (Fig. 14F, item 1416) and a plurality of first upper surface connection pads (Fig. 14F, item 1419), and a first base insulating layer (Fig. 14F, at least items 1413 and 1414) surrounding the plurality of first distribution patterns (Fig. 14F, at least items 1413 and 1414 surround the first distribution patterns);
a second distribution structure (Fig. 6, item 607) including a plurality of second distribution patterns (vertically mirrored image of Fig. 14F, at least items 1417 and 1418) disposed between a plurality of second lower surface connection pads (vertically mirrored image of Fig. 14F, item 1419) and a plurality of second upper surface connection pads (vertically mirrored image of Fig. 14F, item 1416), and a second base insulating layer surrounding the plurality of second distribution patterns (vertically mirrored image of Fig. 14F, at least items 1413 and 1414 surround the second distribution patterns);
a semiconductor chip (Fig. 6, item 602) disposed between the first distribution structure and the second distribution structure (Fig. 6, item 602 disposed between items 608 and 607);
an encapsulant (Fig. 6, item 622) filling a space between the first distribution structure and the second distribution structure and surrounding the semiconductor chip (Fig. 6, item 622 fills the space between items 608 and 607 while surrounding item 602); and
a plurality of connection structures (Fig. 6, items 610) penetrates the encapsulant and disposed adjacent to the semiconductor chip (Fig. 6, items 610 penetrate item 622 and are disposed adjacent to item 602),
wherein a connection structure of the plurality of connection structures includes a conductive post (Fig. 10I, item 1005) extending in a vertical direction to electrically connect a first upper surface connection pad of the plurality of first upper surface connection pads (Fig. 10I, item 1005 extends vertically and connects to item 1012) and a second lower surface connection pad of the plurality of second lower surface connection pads (vertically mirrored image of Fig. 10I, item 1005 connects to item 1012).
723 does not teach about a semiconductor package comprising:
wherein the connection structure includes a conductive antioxidant layer covering side surfaces of the conductive post.
036 teaches in Fig. 23 about a semiconductor package comprising:
wherein the connection structure (item 109) includes a conductive antioxidant layer (item 105) covering side surfaces of the conductive post (item 105 covers side surfaces of item 109).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the connection structure and the conductive antioxidant layer of 036 to electrically connect the first and second distribution structures of 723 in order to provide electrical connection and specifically “the barrier film 105 is provided in order to prevent the diffusion of the material comprising the interconnections in the inter-layer insulation film 102 and increase the adhesion with the inter-layer insulation film 102. Particularly, when the interconnection material is copper and the inter-layer insulation film 102 is a silicon oxide film, the copper has a large diffusion coefficient to the silicon oxide film and can be easily oxidized, so this is prevented” as taught by 036 in Col. 15, Ln. 6-13.
Regarding Claim 2. 036 teaches in Fig. 23 about a semiconductor package comprising:
wherein the conductive antioxidant layer (item 105, formed by conductive materials such as “Ta, Ti, TaN, or TiN”, Col. 15, Ln. 2-3) is disposed between the conductive post and the encapsulant (item 105 is disposed between items 109 and 102).
Regarding Claim 3. 036 teaches in Fig. 23 about a semiconductor package comprising:
wherein the conductive antioxidant layer covers the side surfaces and a lower surface of the conductive post (item 105 covers sides and lower surfaces of item 109).
Regarding Claim 4. 036 teaches in Fig. 23 about a semiconductor package comprising:
wherein the conductive antioxidant layer has an upside-down stepped pyramid shape with an open top and a closed bottom (layer item 105 has open top and closed bottom), and
the conductive post has an elongated upside-down stepped pyramid shape filling an inside of the elongated upside-down stepped pyramid shape.
036 does not teach about a semiconductor package comprising:
wherein the conductive antioxidant layer has a cylindrical shell, and
the conductive post has a circular pillar shape filling an inside of the cylindrical shell shape.
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have experimented with different shapes (including cylindrical shell shape) for the connection structure and the antioxidant layer electrically connecting the two vertically adjacent distribution structures, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
Regarding Claim 5. 036 teaches in Fig. 23 about a semiconductor package comprising:
wherein the conductive antioxidant layer has a thickness of about 15 nm (Col. 15, Ln. 3).
036 does not teach about a semiconductor package comprising:
wherein the conductive antioxidant layer has a thickness ranging from 10 nm to 1 µm.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to experiment multiple thickness value ranges for the antioxidant layer, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 6. 723 teaches in Figs. 6 and 10I about a semiconductor package comprising:
wherein first portions of upper surfaces (Fig. 10I, portions of items 1012 closest to the horizontal edges of the upper surface) of the plurality of first upper surface connection pads (Fig. 10I, items 1012) are covered by the encapsulant (items 1012, of Fig. 10I, are covered by the encapsulant shown in Fig. 6).
Regarding Claim 9. 723 teaches in Fig. 10I about a semiconductor package comprising:
wherein each of the first distribution structure and the second distribution structure comprises a redistribution structure formed by performing a redistribution process (item 1003, performs the redistribution process characteristic of a “redistribution structure”, [0319], Ln. 3).
Regarding Claim 10. 723 teaches in Figs. 8I and 10I about a semiconductor package comprising:
wherein the first distribution structure comprises a printed circuit board (Fig. 8I, teaches that connecting structures items 812 “can be further connected to another redistribution layer, … or printed circuit board”, [0303], Ln. 6-8), and
the second distribution structure comprises a redistribution structure formed by a rewiring process (Fig. 10I, item 1003 performs the rewiring process characteristic of a “redistribution structure”, [0319], Ln. 3).
Regarding Claim 11. 723 teaches in Figs. 6,10I,14F,17G and 19C about a semiconductor package comprising:
a first distribution structure (Fig. 6, item 608) including a plurality of first distribution patterns (Fig. 14F, at least items 1417 and 1418) disposed between a plurality of first lower surface connection pads (Fig. 14F, item 1416) and a plurality of first upper surface connection pads (Fig. 14F, item 1419), and a first base insulating layer (Fig. 14F, at least items 1413 and 1414) surrounding the plurality of first distribution patterns (Fig. 14F, at least items 1413 and 1414 surround the first distribution patterns);
a second distribution structure (Fig. 6, item 607) including a plurality of second distribution patterns (vertically mirrored image of Fig. 14F, at least items 1417 and 1418) disposed between a plurality of second lower surface connection pads (vertically mirrored image of Fig. 14F, item 1419) and a plurality of second upper surface connection pads (vertically mirrored image of Fig. 14F, item 1416), and a second base insulating layer surrounding the plurality of second distribution patterns (vertically mirrored image of Fig. 14F, at least items 1413 and 1414 surround the second distribution patterns);
a semiconductor chip (Fig. 6, item 602) disposed between the first distribution structure and the second distribution structure (Fig. 6, item 602 disposed between items 608 and 607), wherein a plurality of chip pads (Fig. 19C, items 1921) is disposed on a bottom surface of the semiconductor chip (Fig. 19C, items 1921 are disposed on a bottom surface of item 1901);
a plurality of connection structures (Fig. 6, items 610) connecting a first group of the plurality of first upper surface connection pads to a first group of the plurality of second lower surface connection pads (Fig. 6, items 610 connect a group of items 1419 from Fig. 14F and vertically mirrored Fig. 14F respectively) and disposed adjacent to the semiconductor chip (Fig. 6, items 610 are disposed adjacent to item 602), wherein a connection structure of the plurality of connection structures includes a conductive post extending (Fig. 10I, item 1005) in a vertical direction (Fig. 10I, item 1005 extends vertically);
a plurality of chip connection members (Fig. 17G, item 1734) connecting a second group (Fig. 10I, group of items 1012 connected the semiconductor chip) of the plurality of first upper surface connection pads and the plurality of chip pads (Fig. 17G, item 1733); and
an encapsulant (Fig. 6, item 622) surrounding the plurality of connection structures and the semiconductor chip, filling a space among the first distribution structure, the second distribution structure (Fig. 6, item 622 surrounds items 610 and 602, and fills the space between items 608 and 607).
723 does not teach about a semiconductor package comprising:
a conductive antioxidant layer covering side surfaces of the conductive post; and
an encapsulant surrounding the conductive antioxidant layer and spaced apart from the conductive post.
036 teaches in Fig. 23 about a semiconductor package comprising:
a conductive antioxidant layer (item 105) covering side surfaces of the conductive post (item 105 covers side surfaces of item 109); and
an encapsulant (item 102) surrounding the conductive antioxidant layer and spaced apart from the conductive post (item 102 surrounds item 105, and item 102 is spaced apart from item 109).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the connection structure and the conductive antioxidant layer of 036 to electrically connect the first and second distribution structures of 723 in order to provide electrical connection and specifically “the barrier film 105 is provided in order to prevent the diffusion of the material comprising the interconnections in the inter-layer insulation film 102 and increase the adhesion with the inter-layer insulation film 102. Particularly, when the interconnection material is copper and the inter-layer insulation film 102 is a silicon oxide film, the copper has a large diffusion coefficient to the silicon oxide film and can be easily oxidized, so this is prevented” as taught by 036 in Col. 15, Ln. 6-13.
Regarding Claim 12. 723 teaches in Figs. 6 and 10I about a semiconductor package comprising:
wherein first portions of upper surfaces and portions of side surfaces (Fig. 10I, portions of items 1012 closest to the horizontal edges of the upper surface and side edges) of the first group of the plurality of first upper surface connection pads (Fig. 10I, items 1012) are covered by the encapsulant (items 1012, of Fig. 10I, are covered by the encapsulant shown in Fig. 6).
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Fig. 10I, annotated by Examiner from Lou et al., “723”
Regarding Claim 16. 723 teaches in Fig. 10I about a semiconductor package comprising:
wherein the plurality of first upper surface connection pads protrudes from an upper surface of the first base insulating layer (items 1012 protrude from an upper surface of the insulating layer of item 1003), and
wherein a lower surface of the plurality of second lower surface connection pads and a lower surface of the second base insulating layer are coplanar with each other (a lower surface of the insulating layer from a redistribution layer item 1003 and the lower connection pads are coplanar with each other).
Regarding Claim 17. 036 teaches in Fig. 23 about a semiconductor package comprising:
wherein an upper surface of the encapsulant (upper surface of item 102), an uppermost surface of the conductive antioxidant layer (upper surface of item 105), and an upper surface of the conductive post (upper surface of item 109) are at a same vertical level and are coplanar with each other (upper surfaces of items 102,105, and 109 are coplanar with each other).
Regarding Claim 18. 723 teaches in Figs. 6,9E,10I, 14F and 17G about a semiconductor package comprising:
a first redistribution structure (Fig. 6, item 608) including a plurality of first distribution patterns (Fig. 14F, at least items 1417 and 1418) disposed between a plurality of first lower surface connection pads (Fig. 14F, item 1416) and a plurality of first upper surface connection pads (Fig. 14F, item 1419), and a first redistribution insulating layer (Fig. 14F, at least items 1413 and 1414) adjacent to the plurality of first distribution patterns (Fig. 14F, at least items 1413 and 1414 are adjacent the first distribution patterns);
a semiconductor chip (Fig. 6, item 602) disposed on the first redistribution structure (Fig. 6, item 602 disposed on item 608), wherein a plurality of chip pads is disposed on a bottom surface of the semiconductor chip (Fig 17G, items 1733);
a second redistribution structure (Fig. 6, item 607) disposed on the semiconductor chip and the first redistribution structure (Fig. 6, item 607 is disposed on items 602 and 608), and is spaced apart from the semiconductor chip in a vertical direction (Fig. 6, item 607 is spaced apart from item 602 in a vertical direction), wherein the second redistribution structure includes a plurality of second redistribution patterns (vertically mirrored image of Fig. 14F, at least items 1417 and 1418) including a plurality of second lower surface connection pads (vertically mirrored image of Fig. 14F, item 1419), a plurality of second upper surface connection pads (vertically mirrored image of Fig. 14F, item 1416), and a second redistribution insulating layer adjacent to the plurality of second redistribution patterns (vertically mirrored image of Fig. 14F, at least items 1413 and 1414 are adjacent to the second distribution patterns);
a plurality of connection structures (Fig. 6, items 610) disposed adjacent to the semiconductor chip (Fig. 6, items 610 are disposed adjacent to item 602) and connecting a first portion of the plurality of first upper surface connection pads to the plurality of second lower surface connection pads (item 1005 connects to items 1012 of Fig. 10I and of vertically mirrored Fig. 10I), wherein a connection structure of the plurality of connection structures includes a conductive post extending in the vertical direction (Fig. 10I, item 1005 is a conductive post extending in a vertical direction);
a plurality of chip connection members (Fig. 17G, item 1734) connecting a second portion of the plurality of first upper surface connection pads (Fig. 10I, group of items 1012 connected the semiconductor chip) to the plurality of chip pads, wherein a chip connection member (Fig. 9E, item 912) of the plurality of chip connection members includes an under bump metal (UBM) layer (Fig. 9E, item 910) disposed on the plurality of chip pads (Fig. 9E, item 908) and a conductive cap covering the UBM layer;
a plurality of external connection terminals (Fig. 6, items 620) respectively connected to the plurality of first lower surface connection pads (Fig. 6, items 620 are connected to a first lower surface of item 608); and
an encapsulant (Fig. 6, items 622) in a space between the first redistribution structure and the second redistribution structure, covering the plurality of connection structures, and the semiconductor chip (Fig. 6, item 622 fills the space between items 608 and 607 while also covering items 610 and 602).
723 does not teach about a semiconductor package comprising:
a conductive antioxidant layer covering side surfaces and a lower surface of the conductive post;
an encapsulant covering the conductive antioxidant layer, and spaced apart from the conductive post.
036 teaches in Fig. 23 about a semiconductor package comprising:
a conductive antioxidant layer (item 105) covering side surfaces and a lower surface of the conductive post (item 105 covers side and lower surfaces of item 109);
an encapsulant (item 102) covering the conductive antioxidant layer, and spaced apart from the conductive post (item 102 covers item 105, and item 102 is spaced apart from item 109).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the invention was made, to consider utilizing the connection structure and the conductive antioxidant layer of 036 to electrically connect the first and second distribution structures of 723 in order to provide electrical connection and specifically “the barrier film 105 is provided in order to prevent the diffusion of the material comprising the interconnections in the inter-layer insulation film 102 and increase the adhesion with the inter-layer insulation film 102. Particularly, when the interconnection material is copper and the inter-layer insulation film 102 is a silicon oxide film, the copper has a large diffusion coefficient to the silicon oxide film and can be easily oxidized, so this is prevented” as taught by 036 in Col. 15, Ln. 6-13.
Regarding Claim 19. 036 teaches in Fig. 23 about a semiconductor package comprising:
wherein the conductive antioxidant layer comprises a metal, an alloy, or conductive metal nitride (“barrier film 105 is formed by a material such as Ta, Ti, TaN, or TiN”, Col. 15, Ln. 2-3).
Regarding Claim 20. 723 teaches in Figs. 6,9E,10I, 14F and 17G about a semiconductor package comprising:
wherein the encapsulant comprises a mold compound including a filler (“molding material 622 can be filled between the redistribution layer 607 and the redistribution layer 608”, [0287], Ln. 8-10).
723 does not teach about a semiconductor package comprising:
wherein the encapsulant comprises an epoxy mold compound including a filler.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to look to analogous art teaching(s) of alternative suitable or useful material such as an epoxy material, as the selection of a known material based on its suitability for intended purpose deemed obvious. See MPEP 2144.07
Allowable Subject Matter
Claims 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897