DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on March 06, 2026 is acknowledged.
Claims 1-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 06, 2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
liquified solder material that fills the one or more grooves during the soldering process forms a meniscus of claim 13
lack of markers or indicators to show an intersection angle between sidewalls of the one or more grooves is between 50° and 70° of claim 16
lack of markers or indicators to show the one or more grooves have a depth of between 20 µm and 50 µm of claim 17
phase terminal connection and load terminals of claim 19
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation "one or more of the leads" in 5. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner will interpret this to mean “one or more of the plurality of leads.”
Claims 20 would also be rejected as it is dependent on claim 19.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yuferev et. al. (US 20220122906 A1), hereinafter Yuferev, in view of Yoshiba et. al. (JP 2012033756 A), hereinafter Yoshiba.
Regarding claim 11, Yuferev teaches a method of forming a semiconductor package (Fig 21 package 100, [0109]), the method comprising: providing a carrier (Fig 21 carrier 120, [0095]) comprising a die pad (See annotated figure) and a plurality of leads (See annotated figure); providing first (Fig 21 first transistor chip 102, [0110]) and second semiconductor dies (Fig 21 second transistor chip 106, [0110]), each being configured as vertical power devices (the transistor chips may be IGBTs, [0034]), providing an electrical interconnect clip (Fig 21 first clip 122, [0111]) that comprises a die interface portion (See annotated figure) and a carrier connection portion (See annotated figure); proving a stacked die arrangement (Fig 21) on the die pad (See annotated figure) that comprises the die interface portion (See annotated figure) of the electrical interconnect clip (Fig 21 first clip 122, [0111]) arranged between the first (Fig 21 first transistor chip 102, [0110]) and second semiconductor dies (Fig 21 second transistor chip 106, [0110]) and the carrier connection portion (See annotated figure) contacting ([0096]) the carrier (Fig 21 carrier 120, [0095]); providing solder material (Fig 21 solder structure 164, [0100]) in between (Fig 21) the second semiconductor die (Fig 21 second transistor chip 106, [0110]) and the die interface portion (See annotated figure) of the electrical interconnect clip (Fig 21 first clip 122, [0111]); and performing a soldering process (Fig 12 reflow soldering block 226, [0107]) that liquifies the solder material (Fig 21 solder structure 164, [0100]).
Yuferev fails to teach the electrical interconnect clip (Fig 21 first clip 122, [0111]) comprises a solder retention feature that forms a border surrounding the second semiconductor die (Fig 21 second transistor chip 106, [0110]), and wherein the solder retention feature interacts with liquified solder during the soldering process by retaining the solder material (Fig 21 solder structure 164, [0100]) within a confined space that surrounds the second semiconductor die (Fig 21 second transistor chip 106, [0110]), thereby preventing floating movement of the second semiconductor die (Fig 21 second transistor chip 106, [0110]).
However, Yoshiba teaches a carrier (Fig 2 island 14, [0034] of translation) with a groove (Fig 2 groove 15, [0042] of translation). The groove prevents excess solder from overflowing ([0051] of translation). One having ordinary skill in the art before the effective filing date of the claimed invention could have combined the electrical interconnect clip of Yuferev with groove of Yoshiba, as each element performs the same function as it does separately and the results of the combination would have been predictable. Further, the combination would have yielded predictable results, such as the groove of Yoshiba preventing excess solder from moving off the electrical interconnect clip Yuferev. MPEP 2143(I)(A)
Once Yuferev has been modified the electrical interconnect clip (Yuferev: Fig 21 first clip 122, [0111]) comprises a solder retention feature (Yoshiba: Fig 2 groove 15, [0042] of translation) that forms a border surrounding (Yoshiba: Fig 2 the groove 15 surrounds the semiconductor element 18) the second semiconductor die (Yoshiba: Fig 2 semiconductor element 18, [0052] of translation corresponds to Yuferev: Fig 21 second transistor chip 106, [0110]), and wherein the solder retention feature (Yoshiba: Fig 2 groove 15, [0042] of translation) interacts with liquified solder during the soldering process (Yuferev: Fig 12 reflow soldering block 226, [0107]) by retaining the solder material (Yuferev: Fig 21 solder structure 164, [0100]) within a confined space that surrounds the second semiconductor die (Yoshiba: Fig 2 semiconductor element 18, [0052] of translation corresponds to Yuferev: Fig 21 second transistor chip 106, [0110]), thereby preventing floating movement (Yoshiba: positional shift, [0072] of translation) of the second semiconductor die (Yoshiba: Fig 2 semiconductor element 18, [0052] of translation corresponds to Yuferev: Fig 21 second transistor chip 106, [0110]).
The recitation calling for the solder retention feature retaining solder material thereby preventing floating movement of the second semiconductor die does not distinguish over the cited reference regardless of the function allegedly performed by the claimed device, because only the device per se is relevant, no matter which of the device’s functions is referred to in the claim, and if the prior art structure is capable of performing the intended function, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967). In the instant application, the solder retention feature does not differentiate from the claimed device of Yuferev/Yoshiba since it requires interacting with the solder material and retaining it in a space surrounding a semiconductor die.
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Regarding claim 12, Yuferev as modified in claim 11 teaches the solder retention feature (Yoshiba: Fig 2 groove 15, [0042] of translation) is formed by one or more grooves (Yoshiba: Fig 2 groove 15, [0042] of translation) in an upper mating surface (Yoshiba: Fig 2 surface region AR, [0044] of translation corresponds to Yuferev: upper surface of the die interface portion) of the die interface portion (See annotated figure of claim 11) that are spaced apart from outer edge sides of the electrical interconnect clip (Yuferev: Fig 21 first clip 122, [0111]) and form a border surrounding a die attach area (Yoshiba: Fig 2 region AR, [0044] of translation corresponds to Yuferev: die interface portion in annotated figure of claim 11) of the upper mating surface (Yoshiba: Fig 2 surface region AR, [0044] of translation corresponds to Yuferev: upper surface of the die interface portion), and wherein the one or more grooves (Yoshiba: Fig 2 groove 15, [0042] of translation) become at least partially filled by (Yoshiba: [0051] of translation) the liquified solder material (Yoshiba: conductive adhesive material, [0069] of translation corresponds to Yuferev: Fig 21 solder structure 164, [0100]) during the soldering process (Yuferev: Fig 12 reflow soldering block 226, [0107]).
Regarding claim 13, Yuferev as modified in claim 12 teaches the liquified solder material (Yuferev: Fig 21 solder structure 164, [0100]) that fills the one or more grooves (Yoshiba: Fig 2 groove 15, [0042] of translation) during the soldering process forms a meniscus (See annotated figure) that prevents the floating movement (Yoshiba: positional shift, [0072] of translation) of the second semiconductor die (Yuferev: Fig 21 second transistor chip 106, [0110]) during the soldering process.
The recitation calling for the grooves preventing the floating movement of the second semiconductor die does not distinguish over the cited reference regardless of the function allegedly performed by the claimed device, because only the device per se is relevant, no matter which of the device’s functions is referred to in the claim, and if the prior art structure is capable of performing the intended function, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967). In the instant application, the grooves feature does not differentiate from the claimed device of Yuferev/Yoshiba since it requires interacting with the solder material and retaining it in a space surrounding a semiconductor die.
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Regarding claim 14, Yuferev as modified in claim 12 teaches the solder retention feature (Yoshiba: Fig 2 groove 15, [0042] of translation) is formed by a continuous one of the grooves that forms an enclosed shape (Yoshiba: Fig 1) around the upper mating surface (Yoshiba: Fig 2 surface region AR, [0044] of translation corresponds to Yuferev: upper surface of the die interface portion).
Regarding claim 15, Yuferev as modified in claim 12 teaches the one or more grooves (Yoshiba: Fig 2 groove 15, [0042] of translation) have v-shaped cross- sectional geometry (Yoshiba: Fig 2, [0066] of translation).
Regarding claim 16, Yuferev as modified in claim 15 fails to teach an intersection angle between sidewalls of the one or more grooves is between 50° and 70°.
However, Yoshiba teaches that one side of the groove 15 is to be positioned to prevent excessive spreading of molten solder ([0068] of translation). Further, Yoshiba teaches the area enclosed by the grooves is chosen to ensure that when the solder spreads there is sufficient fixing of the semiconductor chip to prevent positional shifting ([0072]). In addition, Yoshiba teaches the groove is formed by etching or pressing ([0066] of translation). The dimensions of the v-shaped groove and subsequent intersection angle is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to vary, through routine optimization, the intersection angle of the sidewalls of the one or more grooves as Yoshiba has identified the intersection angle as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at an intersection angle between sidewalls of the one or more grooves is between 50° and 70°, in order to achieve the desired balance between the amount of overflow on the side of the semiconductor chip and the amount of processing to form the one or more grooves, as taught by Yoshiba. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed intersection angle is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 17, Yuferev as modified in claim 12 fails to teach the one or more grooves have a depth of between 20 µm and 50 µm.
However, Yoshiba teaches the depth of the groove is shallower than the thickness of the island with an example based on the thickness of the island ([0066] of translation). Further, Yoshiba teaches the groove is formed by etching or pressing ([0066] of translation). The depth of the one or more grooves is therefore a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to vary, through routine optimization, the depth of the groove as Yoshiba has identified the depth of the groove as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a depth of the one or more grooves between 20 µm and 50 µm, in order to achieve the thickness of the island and the processing time to produce the groove, as taught by Yoshiba. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed depth is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 18, Yuferev as modified in claim 12 the die attach area (Yoshiba: Fig 2 region AR, [0044] of translation corresponds to Yuferev: die interface portion in annotated figure of claim 11) of the upper mating surface (Yoshiba: Fig 2 surface region AR, [0044] of translation corresponds to Yuferev: upper surface of the die interface portion) is a bare surface of the base metal (Examiner notes that Yuferev and Yoshiba do not teach adding additional materials between the solder and clip/substrate; One having ordinary skill in the art before the effective filing date of the claimed invention would recognize this as being a bare surface of the base metal).
Yuferev as modified in claim 12 fails to teach the electrical interconnect clip is formed from a base metal of copper, aluminum, or alloys thereof.
Regarding the choice to have the electrical interconnect clip to be formed from a base metal of copper, aluminum, or alloys thereof. Yuferev teaches the electrical interconnect clip (Fig 21 first clip 122, [0111]) is metallic ([0049]). Further, Yuferev teaches the package should have good electrical and thermal performance ([0030]). Yoshiba teaches a base metal of copper (Fig 2 island 14 made of copper, [0034] of translation). One having ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use copper because it would provide the desired electrical and thermal performance desired of Yuferev. That is, "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103." KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421.
Regarding claim 19, Yuferev as modified in claim 11 teaches the first (Yuferev: Fig 21 first transistor chip 102, [0110]) and second semiconductor dies (Yuferev: Fig 21 second transistor chip 106, [0110]) are each configured as discrete transistor dies (Yuferev: [0034]), wherein the first (Yuferev: Fig 21 first transistor chip 102, [0110]) and second semiconductor dies (Yuferev: Fig 21 second transistor chip 106, [0110]) are arranged in a half-bridge configuration (Yuferev: [0065]), and wherein the electrical interconnect clip (Yuferev: Fig 21 first clip 122, [0111]) forms a phase terminal connection (Yuferev: [0096]) that electrically connects (Yuferev: [0096]) load terminals (Yuferev: Fig 20 source pads 104/108, [0096] and Fig 1 source pads 104/108, [0096]) from the first (Yuferev: Fig 21 first transistor chip 102, [0110]) and second semiconductor dies (Yuferev: Fig 21 second transistor chip 106, [0110]) to one or more of the leads (See annotated figure of claim 11).
Regarding claim 20, Yuferev as modified in claim 19 teaches a second electrical interconnect clip (Yuferev: Fig 21 second clip 124, [0097]) and electrically connecting (Yuferev: [0097]) a second load terminal (Yuferev: Fig 20 drain pad 118, [0097]) of the second semiconductor die (Yuferev: Fig 21 second transistor chip 106, [0110]) with the carrier (Yuferev: Fig 21 carrier 120, [0095]) via the second electrical interconnect clip (Yuferev: Fig 21 second clip 124, [0097]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Herbsommer et. al. (US 20120248521 A1) teaches a module having a stacked FET configuration connected with an additional IC.
Yilmaz et. al. (US 8952509 B1) teaches a stacked multi chip device
Denison et. al. (US 20140306332 A1) teaches a stacked die device with an additional IC
Huang (CN 204732400 U) teaches a v-shaped groove that surrounds a semiconductor chip to prevent solder spreading on a base
Fuji (US 20220148944 A1) teaches a groove that surrounds a semiconductor chip to prevent solder spreading on a base
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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