DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 3/4/2026.
Applicant's election with traverse of Group I in the reply filed on 3/4/2026 is acknowledged. The traversal is on the ground(s) that there would be no serious or undue burden on the Examiner. This is not found persuasive because as defined within the previous Office Action, these particular claims fall under a different classification such that it would require separate searching fields criteria.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gheewala et al. (US 6,617,621).
In regards to claim 1, Gheewala discloses of an integrated circuit (IC), comprising: at least one of an XOR or XNOR circuit comprising at least two cells (for example see Figs 6E, 15, 3-cell XOR and XNOR respectively), wherein the two cells overlap such that each of the two cells share at least one net (see Figs 6E, 15, overlap and share power nets), wherein there is no dummy gate between or in either of the two cells (see Figs 6E, 15 and Column 9 Line 65 – Column 10 Line 12, Column 14 Lines 49-59).
In regards to claim 2, Gheewala discloses of the IC of claim 1, wherein the two cells share at least two nets (see Figs 6E, 15, two shared net supplies).
In regards to claim 11, Gheewala discloses of a system, comprising: an IC (see Fig 1), comprising: at least one of an XOR or XNOR circuit comprising at least two cells (for example see Figs 6E, 15, 3-cell XOR and XNOR respectively), wherein the at least two cells overlap, wherein there is no dummy gate between or in either of the two cells (see Figs 6E, 15); and a memory (for example see 130 in Fig 1) communicatively coupled to the IC (for example see Fig 1, 6E, 15 and Column 9 Line 65 – Column 10 Line 12, Column 14 Lines 49-59).
In regards to claim 12, Gheewala discloses of the system of claim 11, wherein the at least two cells overlap by sharing at least one net (for example see Figs 6E, 15, overlap sharing power nets).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gheewala et al. (US 6,617,621).
In regards to claim 10, Gheewala discloses of the IC of claim 1 as found within the explanation above.
However. Gheewala does not explicitly disclose of wherein the at least two cells are formed using a 3nm process or smaller.
One having ordinary skill in the art would readily recognize the various fabrication processing since such a modification would have involved a mere size change of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. (see In re Rose, 105 USPQ 237 (CCPA 1955))
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the cells formed using a 3nm process or smaller as an obvious matter of design choice to adhere to the client’s specifications and/or limitations for the device.
Allowable Subject Matter
Claims 3-9 and 13-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 3, the prior art does not disclose of the IC of claim 1, wherein each of the at least two cells comprises a plurality of active gates, wherein there is no dummy gate between or in either of the at least two cells, wherein a pitch between two adjacent active gates is less than 50 nm, nor would it have been obvious to one of ordinary skill in the art to do so. Claim 4 is also objected to as being dependent on claim 4.
In regards to claim 5, the prior art does not disclose of the IC of claim 1, wherein the IC comprises the XOR circuit, wherein the at least two cells comprise a NOR cell and an AND-OR-INVERTED (AOI) cell that share the at least one net, nor would it have been obvious to one of ordinary skill in the art to do so. Claim 6 is also objected to as being dependent on claim 5.
In regards to claim 7, the prior art does not disclose of the IC of claim 1, wherein the IC comprises the XNOR circuit, wherein the at least two cells comprise a NAND cell and an OR-AND-INVERTED (OAI) cell that share the at least one net, nor would it have been obvious to one of ordinary skill in the art to do so. Claim 8 is also objected to as being dependent on claim 7.
In regards to claim 9, the prior art does not disclose of the IC of claim 1, wherein the at least one net is a virtual VDD, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 13, the prior art does not disclose of the system of claim 11, wherein each of the at least two cells comprises a plurality of active gates, wherein a pitch between two adjacent active gates is less than 50 nm, nor would it have been obvious to one of ordinary skill in the art to do so.
In regards to claim 14, the prior art does not disclose of the system of claim 11, wherein the system comprises the XOR circuit, wherein the at least two cells comprise a NOR cell and an AOl cell where there is no dummy gate between or in the NOR cell or the AOl cell, nor would it have been obvious to one of ordinary skill in the art to do so. Claim 15 is also objected to as being dependent on claim 14.
In regards to claim 16, the prior art does not disclose of the system of claim 11, wherein the system comprises the XNOR circuit, wherein the at least two cells comprise a NAND cell and an OAI cell where there is no dummy gate between or in the NAND cell or the OAI cell, nor would it have been obvious to one of ordinary skill in the art to do so. Claim 17 is also objected to as being dependent on claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason M Crawford whose telephone number is (571)272-6004. The examiner can normally be reached Mon-Fri 6:00am-3:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON M CRAWFORD/Primary Examiner, Art Unit 2844
Prosecution Insights