DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5-7, 9, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20190164945 (Chae et al) in view of US 20050199891 (Kunisato et al) and US 20210202815 (Jang et al, hereafter referred to as Jang’815).
Concerning claim 1, Chae discloses a light emitting device, comprising (Figs. 55-57)
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a substrate (451) ([0638]); a first LED stack (423) disposed on the substrate, and including a first conductivity type semiconductor layer (423a), an active layer ([0640]), and a second conductivity type semiconductor layer (423b) . . .; a second LED stack (433) disposed between the substrate and the first LED stack (Fig. 56), and including a first conductivity type semiconductor layer (433a), an active layer ([0640]), and a second conductivity type semiconductor layer (433b); a third LED stack (443) disposed between the substrate and the second LED stack (Fig. 56); and including a first conductivity type semiconductor layer (433a), an active layer ([0640]), and a second conductivity type semiconductor layer (433b); a lower insulation layer (461) covering the first through third LED stacks ([0693]); an upper insulation layer (481) disposed on the lower insulation layer (Fig. 56 and [00698]); and electrode pad layers (471, 473, 475, and 477ab) disposed on the upper insulation layer, and electrically connected to the first through third LED stacks (Fig. 56 and 57), wherein: the lower insulation layer has openings (461a, 461b, 461c, 461d, and 461e) allowing electrical connection to the first through third LED stacks (Fig. 56 right side), the upper insulation layer covers the lower insulation layer such that each of the openings of the lower insulation layer is at least partially exposed (Fig. 56 and [0698]), and the electrode pad layers extend on the upper insulation layer to pass through openings in the lower insulation layer (Fig. 56 and [0698]).
Chae does not disclose (according to the embodiment as shown in Figs. 55-57) the first LED stack having a roughened surface disposed toward the substrate or the lower insulation layer and the upper insulation layer are disposed between the substrate and the electrode pad layers. However, Kunisato discloses a light emitting device configuration (Figs. 22-30) Specifically, the exposed surface of the p-type contact layer 73 is thereafter textured by photolithography and dry etching. At this time, the surface of the p-type contact layer 73 is so textured that the width of a portion between the centers of the adjacent projecting and recess portions of the textured surface of the p-type contact layer 73 is about 0.1 .mu.m to about 50 .mu.m and the height of the projecting portions from the bottoms of the recess portions is about 1 nm to about 2 .mu.m. ([0104]). Subsequently, the conductive substrate 71 is bonded onto the upper surface of the p-side electrode 72 through a process similar to that of the first embodiment shown in FIG. 4. Thereafter the Si substrate 91 and the buffer layer 92 are removed by wet etching with a hot phosphoric acid solution or the like yielding the structure of Fig. 27 with a textured nitride semiconductor layer facing towards the substrate. Kunisato discloses that such a configuration provides a nitride-based semiconductor light-emitting device capable of improving light extraction efficiency ([0011]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the structure of Chae to have a roughened surface disposed toward the substrate as disclosed by Kunisato in order to improve light extraction efficiency.
Additionally, Jang’815 discloses a light emitting device embodiment (Figs. 1A-1C)
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in which the configuration of the light emitting device is altered such that the lower insulation layer (81) and an upper insulation layer (83) are disposed between the substrate (11) and the electrode pad layers (20pd, 40pd, and 50pd) (rectangular enclosed portions in annotated Fig. 1C above). Jung discloses at least one of the first, second, and third insulation layers 81, 83, and 85 may include a distributed Bragg reflector (DBR) which can allow for a structure that can emit/block light in desired portions of the device ([0068]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Chae such that the lower insulation layer and the upper insulation layer are disposed between the substrate and the electrode pad layers as disclosed by Jang’815 in order to form a structure that has the ability to emit/block light in desired portions of the device.
Continuing to claim 2, Chae in view of Kunisato and Jang’815 discloses wherein one of the electrode pad layers (Chae 477ab) passes through a plurality of openings of the lower insulation layer to be commonly electrically connected to the first conductivity type semiconductor layers of the first through third LED stacks (Chae Fig. 56).
Regarding claim 5, Chae in view of Kunisato and Jang’815 discloses wherein three of the electrode pad layers (Chae 471, 473, and 477ab) are electrically connected to second conductivity type semiconductor layers of the first through third LED stacks, respectively, through different openings of the lower insulation layer (Chae Figs. 56 and 57).
Pertaining to claim 6, Chae in view of Kunisato and Jang’815 discloses further comprising: transparent electrode layers (Chae 445 and 435) respectively disposed on the second conductivity type semiconductor layers of the first through third LED stacks (Chae [0654]), wherein three of the electrode pad layers are connected to the transparent electrode layers, respectively (Chae Fig. 56).
As to claim 7, Chae in view of Kunisato and Jang’815 discloses wherein the upper insulation layer has openings corresponding to the openings in the lower insulation layer (Chae [0698]).
Concerning claim 9, Chae in view of Kunisato and Jang’815 discloses wherein at least one of the electrode pad layers includes a curved upper surface (Chae circled portion in annotated Fig. 56 above).
Continuing to claim 10, Chae in view of Kunisato and Jang’815 discloses wherein each of the electrode pad layers extends toward a center and an outside of the light emitting device from the opening of the lower insulation layer, and at least one electrode pad layer extends more lengthily to the outside of the light emitting device than to the center of the light emitting device from the opening of the lower insulation layer (Chae Fig. 55).
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190164945 (Chae et al) in view of US 20050199891 (Kunisato et al) and US 20210202815 (Jang et al, hereafter referred to as Jang’815), as applied to claim 1 above and further in view of US 20210057481 (Chae et al, hereafter referred to as Chae’481)
Considering claim 3, Chae in view of Kunisato and Jang’815 discloses further comprising: an ohmic contact layer (Chae 425) disposed on . . .the first conductivity type semiconductor layer of the first LED stack (Chae [0667]-[0668]) . . . , wherein one of the electrode pad layers (Chae 477ab) is connected to the ohmic contact layer (Chae Fig. 56).
Chae in view of Kunisato and Jang’815 does not disclose the ohmic contact layer is disposed on an entirety of a surface of the first conductivity type semiconductor layer of the first LED or that it is formed on a side opposite the substrate. However Chae’481 discloses a light emitting device configuration
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in which an ohmic layer (62) is formed on an entirety of the central surface of the first conductivity type semiconductor layer (23a) of the first LED stack (23) on a side opposite the substrate (41) ([0089]). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). MPEP 2144.04 IV. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Chae in view of Kunisato and Jang’815 in view of the configuration of Chae’481 absent evidence that such configuration is significant.
Referring to claim 4, Chae in view of Kunisato, Jang’815, and Chae’481 disclose wherein one of the electrode pad layers (Chae 471 and 473) directly contacts the first conductivity type semiconductor layers of the second LED stack and the third LED stack (Chae Fig. 57, note that each electrode pad contacts one of the first conductivity type semiconductor layer of the third and the second LED stacks).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190164945 (Chae et al) in view of US 20050199891 (Kunisato et al) and US 20210202815 (Jang et al, hereafter referred to as Jang’815), as applied to claim 1 above and further in view of US 20210384181 (Xu et al).
As to claim 8, Chae in view of Kunisato and Jang’815 discloses forming a lower and upper insulation layer on the LED stacks (Chae Figs. 56 and 57 and Jang’815 Fig. 1C).
Chae in view of Kunisato and Jang’815 does not disclose wherein a height of an upper most surface of the upper insulation layer is lower than that of an upper most surface of the lower insulation layer. However, Xu discloses an LED stack configuration in which an upper insulation layer (146 and 148) has an upper most height that is formed lower than a height of a lower insulation layer (162) (Fig. 1B, [0184], and [0221]). Xu discloses that such configuration allows for direct bonding or formation of different LED structures and/or other layers together with less destruction to the existing structures within the planarized layers ([0020]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of upper and lower insulation layers of Chae in view of Xu such that a height of an upper most surface of the upper insulation layer is lower than that of an upper most surface of the lower insulation layer in order to allow for direct bonding or formation of different LED structures and/or other layers together with less destruction to the existing structures within the planarized layers.
Claim(s) 11-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190164945 (Chae et al) in view of US 20200365647 (Jang et al) and US 20210202815 (Jang et al hereafter referred to as Jang’815).
Concerning claim 11, Chae discloses . . .the light emitting device, comprising (Figs. 55-57)
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a substrate (451) ([0638]); a first LED stack (423) disposed on the substrate, and including a first conductivity type semiconductor layer (423a), an active layer ([0640]), and a second conductivity type semiconductor layer (423b); a second LED stack (433) disposed between the substrate and the first LED stack (Fig. 56), and including a first conductivity type semiconductor layer (433a), an active layer ([0640]), and a second conductivity type semiconductor layer (433b); a third LED stack (443) disposed between the substrate and the second LED stack (Fig. 56); and including a first conductivity type semiconductor layer (433a), an active layer ([0640]), and a second conductivity type semiconductor layer (433b); a lower insulation layer (461) covering the first through third LED stacks ([0693]); an upper insulation layer (481) disposed on the lower insulation layer (Fig. 56 and [00698]); and electrode pad layers (471, 473, 475, and 477ab) disposed on the upper insulation layer, and electrically connected to the first through third LED stacks (Fig. 56 and 57), wherein: the lower insulation layer has openings (461a, 461b, 461c, 461d, and 461e) allowing electrical connection to the first through third LED stacks (Fig. 56 right side), the upper insulation layer covers the lower insulation layer such that each of the openings of the lower insulation layer is at least partially exposed (Fig. 56 and [0698]), and the electrode pad layers extend on the upper insulation layer to pass through openings in the lower insulation layer (Fig. 56 and [0698]).
Chae does not disclose a light emitting module, comprising: a circuit board with pads; a light emitting device disposed on the circuit board; and bonding layers for bonding the light emitting device to the circuit board or the lower insulation layer and the upper insulation layer are disposed between the substrate and the electrode pad layers.. However, Jang discloses a light emitting module (Fig. 14) that comprises a circuit board (11p) with pads (11pa); a light emitting device (100) disposed on the circuit board; and bonding layers for bonding the light emitting device to the circuit board ([0118]) which are essential parts of forming a display apparatus ([0006] and [0007]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporated a circuit board with pads with the light emitting device of Chae disposed on the circuit board and bonding layers for bonding the light emitting device to the circuit board in order to form a display device as disclosed by Jang.
Additionally, Jang’815 discloses a light emitting device embodiment (Figs. 1A-1C)
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in which the configuration of the light emitting device is altered such that the lower insulation layer (81) and an upper insulation layer (83) are disposed between the substrate (11) and the electrode pad layers (20pd, 40pd, and 50pd) (rectangular enclosed portions in annotated Fig. 1C above). Jung discloses at least one of the first, second, and third insulation layers 81, 83, and 85 may include a distributed Bragg reflector (DBR) which can allow for a structure that can emit/block light in desired portions of the device ([0068]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Chae such that the lower insulation layer and the upper insulation layer are disposed between the substrate and the electrode pad layers as disclosed by Jang’815 in order to form a structure that has the ability to emit/block light in desired portions of the device.
Continuing to claim 12, Chae in view of Jang and Jang’815 discloses wherein the bonding layers bond the electrode pad layers to the pads (Jang Fig. 14 and [0118]).
Considering claim 13, Chae in view of Jang and Jang’815 discloses wherein one of the electrode pad layers (Chae 477ab) passes through a plurality of openings of the lower insulation layer to be commonly electrically connected to the first conductivity type semiconductor layers of the first through third LED stacks (Chae Fig. 56).
Referring to claim 14, Chae in view of Jang and Jang’815 discloses wherein one of the electrode pad layers (Chae 471 and 473) directly contacts the first conductivity type semiconductor layers of the second LED stack and the third LED stack (Chae Fig. 57, note that each electrode pad contacts one of the first conductivity type semiconductor layer of the third and the second LED stacks).
Regarding claim 15, Chae in view of Jang and Jang’815 discloses wherein three of the electrode pad layers (Chae 471, 473, and 477ab) are electrically connected to second conductivity type semiconductor layers of the first through third LED stacks, respectively, through different openings of the lower insulation layer (Chae Figs. 56 and 57).
Pertaining to claim 16, Chae in view of Jang and Jang’815 discloses wherein: the lower insulation layer includes a distributed Bragg reflector ([0693]), and the lower insulation layer contacts the first conductivity type semiconductor layers of the first through third LED stacks (Figs. 56 and 57).
Chae in view of Jang and Jang’815 does not disclose in the embodiment as disclosed in Figs. 55-57 of Chae the lower insulation layer is disposed over substantially all of a surface of the first LED stack opposite the substrate. However Chae discloses a configuration (Fig. 64D)
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in which the lower insulation layer (561) is formed over substantially all of a surface of the first LED stack opposite the substrate (as is seen above). In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). MPEP 2144.04 IV. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Chae in view of Jang and Jang’815 such that Chae the lower insulation layer is disposed over substantially all of a surface of the first LED stack opposite the substrate as disclosed in alternate embodiments of Chae (Fig. 64D) absent evidence that such configuration is significant.
Response to Arguments
Applicant's arguments filed 02/10/26 have been fully considered but they are not persuasive. The Office cites the lower insulation layer 461 and upper insulation layer 481 in FIGS. 56 and 57 of Chae as teaching the lower insulation layer and upper insulation layer of the claimed invention. However, a closer inspection of FIGS. 56 and 57 of Chae would show that its upper insulation layer 481 is shown as covering the entire surface of its light emitting element. As such, Chae cannot be characterized as disclosing that each of the openings of the lower insulation layer is at least partially exposed by the covering of its the upper insulation layer. It is noted that the cited Figs. do not show the openings, however as stated above, [0698] discloses that openings may be formed in the upper insulation layer and is being relied on for this limitation. Therefore the argument is not found to persuasive and the rejection stands.
Applicant’s arguments with respect to claim(s) 1, 3, 11, and 16have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/Examiner, Art Unit 2897 08/13/26
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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