DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: Q288484
Filling Date: 09/18/2023
Priority Date: 02/07/2023
Inventor: Lee et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US 2021/0351079 A1) in view of Chu et al (US 2021/0399099 A1).
Regarding claim 1, Su discloses a semiconductor device (Fig. 2), comprising: a substrate 126, 212 (Paras. 24, 27); a lower power line 122 (Para. 67) buried in a lower portion of the substrate 212; a source/drain pattern 106 (Para. 26) on the substrate; and a backside contact 120 (Para. 66) that penetrates the substrate 126 and electrically couples the lower power line 122 to the source/drain pattern 106, wherein the backside contact 120 comprises: an epitaxial pattern 119 (Fig. 3, Para. 25) coupled to a lower portion of the source/drain pattern 106; a contact plug 218 (Para. 24) coupled to the lower power line 122; and a metal-semiconductor compound layer 121 (Para. 25) between the epitaxial pattern 119 and the contact plug 218, and wherein the epitaxial pattern 119 comprises a top surface that protrudes toward the source/drain pattern 106.
Su does not explicitly disclose a level of a lowermost point of the epitaxial pattern is lower than a level of an upper surface of the substrate.
However, Chu discloses a level of a lowermost point of the epitaxial pattern 260 (Fig. 16, Para. 33) is lower than a level of an upper surface of the substrate 252 (Para. 26). Chu teaches the above modification is used to reduce contact resistance of the device (Para. 4). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Su epitaxial pattern with Chu epitaxial pattern as suggested above to reduce contact resistance of the device (Para. 4).
Regarding claim 2, Su discloses the semiconductor device of claim 1, wherein a concentration of impurities in the epitaxial pattern 119 is greater than a maximum concentration of impurities in the source/drain pattern 106 (Para. 25).
Regarding claim 5, Su discloses the semiconductor device of claim 1, further comprising: a device isolation layer 104b (Para. 25) between the source/drain pattern 106 and the substrate 126, 212, wherein the backside contact 120 penetrates the device isolation layer 118.
Regarding claim 6, Su discloses the semiconductor device of claim 5, further comprising: a liner 118 (Para. 65) between the device isolation layer 104b and the backside contact 120.
Regarding claim 7, Su discloses the semiconductor device of claim 1, wherein the substrate 126, 212 comprises a dielectric substrate (Paras. 24, 27).
Regarding claim 3, Su does not explicitly disclose the semiconductor device of claim 1, wherein: the epitaxial pattern comprises a { 111 } crystal plane, and at least a portion of the epitaxial pattern is covered with the metal-semiconductor compound layer.
However, Su discloses the epitaxial pattern 119 and metal semiconductor compound as claimed impurity concentration (Para. 25).
Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the epitaxial pattern comprises a { 111 } crystal plane, and at least a portion of the epitaxial pattern is covered with the metal-semiconductor compound layer for intended purposes.
the applicants have not established the criticality (see next paragraph below) of the crystal plane.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed crystal plane or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 4, Su does not explicitly disclose the semiconductor device of claim 1, wherein: the source/drain pattern 106 comprises a buffer layer (bottom) and a main layer (top) on the buffer layer, the source/drain pattern comprises silicon-germanium (Para. 22), and at least a portion of the epitaxial pattern 119 is in contact with the main layer 106.
Su does not explicitly disclose a germanium concentration of the main layer is in a range of about 30 at% to about 70 at%.
However, Su discloses a particular percentage of germanium in the SiGe layer 106 (Para. 22).
Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain a germanium concentration of the main layer is in a range of about 30 at% to about 70 at% for intended purposes.
the applicants have not established the criticality (see next paragraph below) of the at%.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed at% or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US 2021/0351079 A1) in view of Chu et al (US 2021/0399099 A1) and further in view of Lee et al (US 2022/0068805 A1).
Regarding claim 8, Su does not explicitly disclose the semiconductor device of claim 1, further comprising: a power delivery network layer below the substrate, wherein the power delivery network layer is configured to provide the lower power line with at least one of a source voltage and a drain voltage.
However, Lee discloses a power delivery network layer BIL2, 160 (Fig. 36, Paras. 171, 170) below the substrate 100 (Para. 171), wherein the power delivery network layer BIL2, 160 (Paras. 171, 170) is configured to provide the lower power line BIL1 (Para. 171) with at least one of a source voltage and a drain voltage (Fig. 36, Para. 171).
Lee teaches the above modification is used to apply power voltage and ground voltage of the device (Para. 171). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Su in view of Chu structure with Lee power delivery network layer as suggested above to apply power voltage and ground voltage of the device (Para. 171).
Allowable Subject Matter
Claims 9-19 and 20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed semiconductor device, comprising: a dielectric substrate; an etch stop layer on the dielectric substrate; a channel pattern on the etch stop layer; wherein the etch stop layer comprises silicon doped with at least one of oxygen (O) and carbon (C), and wherein the etch stop layer is between the dielectric substrate and a lowermost electrode of the plurality of inner electrodes in combination with all other limitations as recited in claim 9.
The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed semiconductor device, comprising: a dielectric substrate; an etch stop layer on the dielectric substrate; a channel pattern on the etch stop layer, the gate capping pattern and is electrically coupled to the gate electrode in combination with all other limitations as recited in claim 16.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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