DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 06/16/2026 has been entered. Applicant's amendment to the Claims
have overcome the 112(b) rejection previously set forth in the Non-Final Office Action dated on 03/16/2026. Claims 1-18 and 22 are pending.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 06/16/2026, have been fully considered. The Applicant’s arguments related to “filling the interconnect opening in the first dielectric layer with polyimide in contact with the first conductive contact layer" and "applying a laser light source to directly convert the polyimide to form a graphene interconnect structure… …persons having ordinary skill in the art would not look to Tour's macro process for laser-scribing commercial polyimide sheet films using a CO2 laser at a power of 3.6 W to modify the sub- micron semiconductor manufacturing processes of Sakamoto and Ham for several reasons. First and foremost, there would be destructive laser interaction from Tour's disclosed approach since exposing an interconnect-defined polyimide filling layer within a delicate micro-scale IC stack to a raw laser beam of the high local power doses described by Tour (e.g., 2.4 W to 5.4 W focused beams) would photothermally vaporize or obliterate the surrounding delicate sub-micron dielectric features, causing catastrophic delamination and thermal stress damage to the active on- wafer semiconductor devices… ….any attempt to invoke Tour's disclosure to remedy the admitted deficiencies from Sakamoto and Ham must fail because Tour's disclosure - of a high-intensity laser scribing to selectively graphitize the outer surface layer of a standalone, macroscopic commercial plastic backing film - nowhere teaches or suggests the polyimide sheet scribing technique by used for an integrated circuit dual-inlaid architecture out of an in-situ localized polymer-to-graphene laser conversion process. The applicant’s arguments are not persuasives because Sakamoto (US 20060091557 A1) and Ham (US 20170358486 A1) disclose filling the interconnect opening in the first dielectric layer with a carbon source in contact with the first conductive layer, then using a thermal treatment to form a graphene interconnect structure ([0085], Ham), Sakamoto and Ham does not disclose in detail the type of carbon source and the thermal treatment used to form a graphene interconnect structure, then, Tour (US 20200112026 A1) disclose a method to form graphene from a polyimide layer using a laser source, this method can be applied to electronic devices, for example such as electrode in [0011]. In addition, Tour ([0006]) includes a list of laser source such as a UV laser source, this also cited by the Applicant in [0018]. Finally, the power of the laser depends of the dimension and design of the electronic device, the Applicant does not include any of these parameters in the claimed invention. The combination of Sakamoto, Ham and Tour results in “filling the interconnect opening in the first dielectric layer with polyimide in contact with the first conductive contact layer" and "applying a laser light source to directly convert the polyimide to form a graphene interconnect structure”.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 8-9,12-17 and 22 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Sakamoto et al. (US 20060091557 A1, of the record) in view of Ham et al. (US 20170358486 A1, hereinafter Ham, of the record) and further in view of Tour et al. (US 20200112026 A1, hereinafter Tour, of the record).
Re: Independent Claim 1, Sakamoto discloses a method for making an integrated circuit interconnect device, comprising:
providing an integrated circuit structure (semiconductor device having an interconnection in [0001], Fig. 8) comprising a first dielectric layer (49,52 interlayer dielectric films 49 and 52 in [0024], Fig. 8) formed over a first conductive contact layer (11 interconnection made of carbon nanotubes in [0050], Fig. 8);
forming an interconnect opening (46,55 connection plug 46, an interconnection trench 55 in [0129,0135], Fig. 8) in the first dielectric layer (49,52) which exposes (Fig. 8c) at least a portion of the first conductive contact layer (11);
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Sakamoto’s Figure 8-Annotated.
Sakamoto does not expressly disclose filling the interconnect opening in the first dielectric layer with polyimide in contact with the first conductive contact layer; and applying a laser light source to directly convert the polyimide to form a graphene interconnect structure in the first dielectric layer which is directly, electrically connected to the first conductive contact layer.
However, in the same semiconductor device manufacturing field of endeavor, Ham discloses filling the interconnect opening (10a-O, 10b-O openings in 10a and in 10b in [0085], Fig. 3) in the first dielectric layer (10a,b substrate as 10 made of insulating material in [0038], Fig. 3) with a carbon source (20a,b [0085], Fig. 3) in contact (Fig. 3) with the first conductive contact layer (30-40 30 made of copper and 40 made of graphene in [0085], Fig. 3); and applying a heat treatment ([0085], Fig. 3) to directly convert the carbon source to form a graphene interconnect structure (40a-40b made of graphene in [0085], Fig. 3) in the first dielectric layer (10a,b) which is directly, electrically connected to the first conductive contact layer (30-40).
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Ham’s Figure 3-portions-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ham’s method of filling the interconnect opening in the first dielectric layer with a carbon source in contact with the first conductive contact layer; and applying a heat treatment to directly convert the carbon source to form a graphene interconnect structure in the first dielectric layer which is directly, electrically connected to the first conductive contact layer to Sakamoto’s method to obtain low-resistance interconnects using high-quality graphene ([0006,0007], Ham).
Still, Sakamoto modified by Ham does not expressly disclose filling the interconnect opening in the first dielectric layer with polyimide; and applying a laser light source to directly convert the polyimide to form a graphene interconnect structure.
However, in the same semiconductor device manufacturing field of endeavor, Tour discloses graphene formation from polyimide applying a laser light source (laser-induced graphene (LIG) formed from commercial polyimide in [0015]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Tour’s method of graphene formation from polyimide applying a laser light source to the combination of Sakamoto and Ham to obtain a more effective method of making graphene-based electronic materials ([0003], Tour).
Re: Claim 2, Sakamoto modified by Ham and Tour discloses the method of claim 1, where providing the integrated circuit structure comprises providing a semiconductor substrate (silicon substrate in [0052], Fig. 8-Annotated, Sakamoto) on which is formed a plurality of integrated circuit elements covered ([0052], Sakamoto) by the first dielectric layer (10 in [0052], Fig. 8-Annotated, Sakamoto).
Re: Independent Claim 8, Sakamoto discloses a method for forming a graphene interconnect structure, comprising:
forming a first conductive layer (11 made of carbon nanotubes in [0050], Fig. 8) over a first dielectric layer (10 insulating layer in [0052], Fig. 8);
forming a second dielectric layer (49,52 interlayer dielectric films 49 and 52 in [0024], Fig. 8) over the first conductive layer (11);
forming a via etch opening (46 connection plug in [0129], Fig. 8) in the second dielectric layer (49,52) which exposes at least a portion of the first conductive layer (11);
forming a wiring line etch opening (55 an interconnection trench in [0135], Fig. 8) in an upper portion of the second dielectric layer (49,52) having a portion which overlaps (Fig. 8c) with the via etch opening (46);
Sakamoto does not expressly disclose forming polyimide to fill the via etch opening and the wiring line etch opening in the second dielectric layer; and applying irradiation from a laser source to directly convert the polyimide into the graphene interconnect structure comprising a graphene wiring line formed in the wiring line etch opening and a graphene via structure formed in the via etch opening to directly, electrically connect the graphene wiring line to the first conductive layer.
However, in the same semiconductor device manufacturing field of endeavor, Ham discloses forming a carbon source to fill (20a,b [0085], Fig. 3) the via etch opening (10a-O opening in 10a in [0085], Fig. 3-Annotated) and the wiring line etch opening (10b-O opening in 10b in [0085], Fig. 3) in the second dielectric layer (10a,b substrate as 10 made of insulating material in [0038, 0085], Fig. 3); and applying heat treatment ([0085], Fig. 3) to directly convert the carbon source (20a,b [0085], Fig. 3) into the graphene interconnect structure (40a-40b made of graphene in [0085], Fig. 3) comprising a graphene wiring line (40b made of graphene in [0085], Fig. 3) formed in the wiring line etch opening (10b-O in [0085], Fig. 3) and a graphene via structure (40a made of graphene in [0085], Fig. 3) formed in the via etch opening (10a-O in [0085], Fig. 3) to directly, electrically connect the graphene wiring line to the first conductive layer (30-40 30 made of copper and 40 made of graphene in [0085], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ham’s method forming a carbon source to fill the via etch opening and the wiring line etch opening in the second dielectric layer; and applying a heat treatment to directly convert the carbon source into the graphene interconnect structure comprising a graphene wiring line formed in the wiring line etch opening and a graphene via structure formed in the via etch opening to directly, electrically connect the graphene wiring line to the first conductive layer to Sakamoto’s method to obtain low-resistance interconnects using high-quality graphene ([0006,0007], Ham).
Still, Sakamoto modified by Ham does not expressly disclose forming polyimide to fill the via etch opening and the wiring line etch opening in the second dielectric layer; and applying irradiation from a laser source to directly convert the polyimide into the graphene interconnect structure.
However, in the same semiconductor device manufacturing field of endeavor, Tour discloses graphene formation from polyimide applying a laser light source (laser-induced graphene (LIG) formed from commercial polyimide in [0015] using a femto-second UV laser source in [0090,0094]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Tour’s method of graphene formation from polyimide applying a laser light source to the combination of Sakamoto and Ham to obtain a more effective method of making graphene-based electronic materials ([0003], Tour).
Re: Claim 9, Sakamoto modified by Ham and Tour discloses the method of claim 8, where forming the first conductive layer (11 in [0050], Fig. 8, Sakamoto) comprises forming a carbon layer on the first dielectric layer (10 in [0052], Fig. 8, Sakamoto) which covers a plurality of integrated circuit elements ([0052], Sakamoto) formed on a semiconductor substrate (silicon substrate in [0052], Fig. 8-Annotated, Sakamoto).
Sakamoto modified by Ham and Tour does not expressly disclose forming the first conductive layer (11 in [0050], Fig. 8, Sakamoto) comprises forming a first graphene layer.
However, in the same semiconductor device manufacturing field of endeavor, Ham discloses forming the first conductive layer (30-40 in [0085], Fig. 3) comprises forming a first graphene layer (40 made of graphene in [0085], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ham’s method forming the first conductive layer comprises forming a first graphene layer to the combination of Sakamoto and Ham and Tour to obtain low-resistance interconnects using high-quality graphene ([0006,0007], Ham).
Re: Claim 12, Sakamoto modified by Ham and Tour discloses the method of claim 8, where forming the via etch opening (46’s Sakamoto in [0129], Fig. 8) in the second dielectric layer (49,52’s Sakamoto, Fig. 8) comprises: patterning a first resist material (53’s Sakamoto, Fig. 8) on the second dielectric layer (49,52’s Sakamoto, Fig. 8) to form a first resist mask (53’s Sakamoto, Fig. 8) with a via opening (53-hole’s Sakamoto, Fig. 8) over the second dielectric layer (49,52’s Sakamoto, Fig. 8); and selectively etching the via etch opening (46’s Sakamoto in [0129], Fig. 8) in the second dielectric layer (49,52’s Sakamoto, Fig. 8) using the via opening (53-hole’s Sakamoto, Fig. 8) in the first resist mask (53’s Sakamoto, Fig. 8).
Re: Claim 13, Sakamoto modified by Ham, Tour and Zhang discloses the method of claim 8, where forming the wiring line etch opening (55’s Sakamoto in [0135], Fig. 8) in the upper portion of the second dielectric layer (49,52’s Sakamoto, Fig. 8) comprises: patterning a second resist material (53’s Sakamoto, Fig. 8) on the second dielectric layer (49,52’s Sakamoto, Fig. 8) to form a second resist mask (53’s Sakamoto, Fig. 8) with a wiring line opening (53-hole’s Sakamoto, Fig. 8) over the second dielectric layer (49,52’s Sakamoto, Fig. 8); and selectively etching the wiring line etch opening (55’s Sakamoto in [0135], Fig. 8) in the second dielectric layer (49,52’s Sakamoto, Fig. 8) using the wiring line opening (53-hole’s Sakamoto, Fig. 8) in the second resist mask (53’s Sakamoto, Fig. 8).
Re: Claim 14, Sakamoto modified by Ham and Tour discloses the method of claim 8, where forming polyimide (Tour applied to Ham and Sakamoto) comprises: filling the via etch opening (10a-O’s Ham in [0085], Fig. 3) and the wiring line etch opening (10b-O’s Ham in [0085], Fig. 3) in the second dielectric layer (10a,b’s Ham in [0085], Fig. 3) with one or more first polyimide (Tour applied to 20a,b’s Ham and Sakamoto) layers.
Sakamoto modified by Ham and Tour does not expressly disclose planarizing the one or more first polyimide layers with a top surface of the second dielectric layer.
However, in the same semiconductor device manufacturing field of endeavor, Ham discloses
planarizing (after S308 and S316, Fig. 3) the one or more carbon source layers with a top surface of the second dielectric layer (10a,b substrate as 10 made of insulating material in [0038, 0085], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ham’s method of planarizing the one or more carbon source layers with a top surface of the second dielectric layer to the combination of Sakamoto and Ham and Tour to obtain low-resistance interconnects using high-quality graphene ([0006,0007], Ham).
Re: Claim 15, Sakamoto modified by Ham and Tour discloses the method of claim 8, where applying irradiation from a laser source (Tour applied to Ham and Sakamoto) comprises: applying a laser irradiation source (Tour applied to Ham and Sakamoto) to one or more first polyimide (Tour applied to Ham and Sakamoto) layers located in the via etch opening (10a-O’s Ham in [0085], Fig. 3) to form the graphene via structure (40a’s Ham in [0085], Fig. 3) in the second dielectric layer (10a,b’s Ham in [0038, 0085], Fig. 3) in direct electrical contact with the first conductive layer (30-40’s Ham in [0085], Fig. 3); and applying a laser irradiation source (Tour applied to Ham and Sakamoto) to one or more second polyimide (Tour applied to Ham and Sakamoto) layers located in the wiring line etch opening (10b-O’s Ham in [0085], Fig. 3) to form the graphene wiring line (40b’s Ham in [0085], Fig. 3) in the second dielectric layer (10a,b’s Ham in [0038, 0085], Fig. 3) which is in direct electrical contact with the graphene via structure (40a’s Ham in [0085], Fig. 3).
Re: Claim 16, Sakamoto modified by Ham and Tour discloses the method of claim 8, where applying irradiation from a laser source comprises: applying irradiation from a femto-second UV laser source (laser-induced graphene formed from commercial polyimide in [0015] using a femto-second UV laser source in [0090,0094]) to directly convert the one or more polyimide layers (Tour, [0015]) into the graphene interconnect structure (40a-40b’s Ham applied to Sakamoto).
Re: Claim 17, Sakamoto modified by Ham and Tour discloses the method of claim 8,
Sakamoto modified by Ham and Tour does not expressly disclose further comprising planarizing the graphene wiring line with a top surface of the second dielectric layer.
However, in the same semiconductor device manufacturing field of endeavor, Ham discloses further comprising planarizing (S316, Fig. 3) the graphene wiring line (40b made of graphene in [0085], Fig. 3) with a top surface of the second dielectric layer (10a,b substrate as 10 made of insulating material in [0038, 0085], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ham’s method of further comprising planarizing the graphene wiring line with a top surface of the second dielectric layer to the combination of Sakamoto and Ham and Tour to obtain low-resistance interconnects using high-quality graphene ([0006,0007], Ham).
Re: Claim 22, Sakamoto modified by Ham and Tour discloses the method of claim 8, where forming polyimide (Tour applied to Ham and Sakamoto) to fill the via etch opening (10a-O’s Ham in [0085], Fig. 3) and the wiring line etch opening (10b-O’s Ham in [0085], Fig. 3) in the second dielectric layer (10a,b’s Ham in [0038, 0085], Fig. 3) comprises: filling the via etch opening (10a-O’s Ham in [0085], Fig. 3) with polyimide (Tour applied to Ham and Sakamoto) using a first deposition process (S310, Fig. 3, Ham) before selectively etching the wiring line etch opening (10b-O’s Ham in [0085], Fig. 3); and filling the wiring line etch opening with polyimide (Tour applied to Ham and Sakamoto) using a second deposition process (S310, S312, Fig. 3, Ham) after selectively etching the wiring line etch opening (10b-O’s Ham in [0085], Fig. 3).
Claim(s) 3,10-11 and 18 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Sakamoto in view of Ham, in view of Tour and further in view of Ng et al. (US 20110268943 A1, hereinafter Ng, of the record).
Re: Claim 3, Sakamoto modified by Ham and Tour discloses the method of claim 1,
Sakamoto modified by Ham and Tour does not expressly disclose where the first dielectric layer comprises an ultra-low-k dielectric layer and where the first conductive contact layer comprises a graphene contact layer.
However, in the same semiconductor device manufacturing field of endeavor, Ham discloses where the first conductive contact layer (30-40 in [0085], Fig. 3) comprises a graphene contact layer (40 made of graphene in [0085], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ham’s method of where the first conductive contact layer comprises a graphene contact layer to the combination of Sakamoto and Ham and Tour to obtain low-resistance interconnects using high-quality graphene ([0006,0007], Ham).
Still, Sakamoto modified by Ham and Tour does not expressly disclose where the first dielectric layer comprises an ultra-low-k dielectric layer.
However, in the same semiconductor device manufacturing field of endeavor, Ng discloses where the first dielectric layer (second layer includes at least fluorine doped diamond-like-carbon in [0007]) comprises an ultra-low-k dielectric layer (in [0007]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ng’s method of where the first dielectric layer comprises an ultra-low-k dielectric layer to the combination of Sakamoto and Ham and Tour to provides a smooth surface, but also has better adhesion to prevent peeling off (Abstract, Ng).
Re: Claim 10, Sakamoto modified by Ham and Tour discloses the method of claim 8, where forming the second dielectric layer (49,52’s Sakamoto, Fig. 8) comprises depositing and planarizing (Sakamoto, Fig. 8) a dielectric layer (49,52’s Sakamoto, Fig. 8) over the first conductive layer (11’s Sakamoto, Fig. 8).
Sakamoto modified by Ham and Tour does not expressly disclose forming the second dielectric layer comprises depositing an ultra-low-k dielectric layer.
However, in the same semiconductor device manufacturing field of endeavor, Ng discloses the second dielectric layer (second layer includes at least fluorine doped diamond-like-carbon in [0007]) comprises depositing an ultra-low-k dielectric layer (in [0007]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ng’s method of forming the second dielectric layer comprises depositing an ultra-low-k dielectric layer to the combination of Sakamoto and Ham and Tour to provides a smooth surface, but also has better adhesion to prevent peeling off (Abstract, Ng).
Re: Claim 11, Sakamoto modified by Ham and Tour discloses the method of claim 10, where the ultra-low-k dielectric layer (Ng applied to Sakamoto) comprises fluorinated amorphous diamond-like carbon (in [0007], Ng).
Re: Claim 18, Sakamoto modified by Ham and Tour discloses the method of claim 8,
Sakamoto modified by Ham and Tour does not expressly disclose where forming the second dielectric layer comprises forming amorphous fluorinated diamond-like carbon (a-C:F).
However, in the same semiconductor device manufacturing field of endeavor, Ng discloses where forming the second dielectric layer (second layer includes at least fluorine doped diamond-like-carbon in [0007]) comprises forming amorphous fluorinated diamond-like carbon (a-C:F) (in [0007]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ng’s method of forming the second dielectric layer comprises forming amorphous fluorinated diamond-like carbon (a-C:F) to the combination of Sakamoto and Ham and Tour to provides a smooth surface, but also has better adhesion to prevent peeling off (Abstract, Ng).
Claim(s) 4-7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Sakamoto in view of Ham, in view of Tour and further in view of Zhang et al. (US 20160163636 A1, hereinafter Zhang, of the record).
Re: Claim 4, Sakamoto modified by Ham and Tour discloses the method of claim 1,
Sakamoto modified by Ham and Tour does not expressly disclose where forming the interconnect opening in the first dielectric layer comprises: patterning a first resist material on the first dielectric layer to form a first resist mask with a via opening over the first dielectric layer; selectively etching the via opening in the first dielectric layer using the first resist mask; patterning a second resist material on the first dielectric layer to form a second resist mask with a metal line opening over the first dielectric layer; and selectively etching the metal line opening in the first dielectric layer using the second resist mask.
However, in the same semiconductor device manufacturing field of endeavor, Zhang discloses where forming the interconnect opening (207-215 openings in [0052,0077], Figs. 6-12) in the first dielectric layer (202 a dielectric layer in [0032], Fig. 6) comprises: patterning a first resist material (205 first photo-resist layer in [0045], Fig. 6) on the first dielectric layer (202) to form a first resist mask (205) with a via opening (an opening in 205, Fig. 6) over the first dielectric layer (202); selectively etching (Fig. 7) the via opening in the first dielectric layer (202) using the first resist mask (205); patterning a second resist material (213 second photo-resist layer in [0065], Fig. 10) on the first dielectric layer (202) to form a second resist mask (213) with a metal line opening (an opening in 213, Fig. 10) over the first dielectric layer (202); and selectively etching (Fig. 12) the metal line opening in the first dielectric layer (202) using the second resist mask (213).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zhang’s method of forming the interconnect opening in the first dielectric layer comprises: patterning a first resist material on the first dielectric layer to form a first resist mask with a via opening over the first dielectric layer; selectively etching the via opening in the first dielectric layer using the first resist mask; patterning a second resist material on the first dielectric layer to form a second resist mask with a metal line opening over the first dielectric layer; and selectively etching the metal line opening in the first dielectric layer using the second resist mask to the combination of Sakamoto and Ham and Tour to reduce the transmission delay of the signal ([0004], Zhang).
Re: Claim 5, Sakamoto modified by Ham, Tour and Zhang discloses the method of claim 4,
Sakamoto modified by Ham, Tour and Zhang does not expressly disclose where filling the interconnect opening comprises: filling the via opening in the first dielectric layer with polyimide using a first deposition process before patterning the second resist material; and filling the metal line opening in the first dielectric layer with polyimide using a second deposition process after selectively etching the metal line opening.
However, in the same semiconductor device manufacturing field of endeavor, Zhang discloses filling the interconnect opening (207-215 openings in [0052,0077], Figs. 6-12) comprises: filling (Figs. 8-9) the via opening (an opening in 205, Fig. 6) in the first dielectric layer (202 a dielectric layer in [0032], Fig. 6) with carbon nanotubes ([0080]) using a first deposition process before patterning (Figs. 8-9) the second resist material (213 second photo-resist layer in [0065], Fig. 10); and filling the metal line opening (an opening in 213, Fig. 10) in the first dielectric layer (202) with a conductive layer ([0082]) using a second deposition process after selectively etching (Fig. 12) the metal line opening (an opening in 213, Fig. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Zhang’s method of where filling the interconnect opening comprises: filling the via opening in the first dielectric layer with carbon nanotubes using a first deposition process before patterning the second resist material; and filling the metal line opening in the first dielectric layer with a conductive layer using a second deposition process after selectively etching the metal line opening to the combination of Sakamoto and Ham and Tour to reduce the transmission delay of the signal ([0004], Zhang).
The combination of Sakamoto modified by Ham, Tour and Zhang results in where filling the interconnect opening comprises: filling the via opening in the first dielectric layer with polyimide using a first deposition process before patterning the second resist material; and filling the metal line opening in the first dielectric layer with polyimide using a second deposition process after selectively etching the metal line opening.
Re: Claim 6, Sakamoto modified by Ham, Tour and Zhang discloses the method of claim 4, where filling the interconnect opening (10a-O,10b-O’s Ham in [0085], Fig. 3) comprises: filling the via opening (10a-O’s Ham in [0085], Fig. 3) and the metal line opening (10b-O’s Ham in [0085], Fig. 3) in the first dielectric layer (10a,b’s Ham in [0085], Fig. 3) with polyimide (Tour applied to Ham and Sakamoto) using a deposition process (Ham 20a and 20b are formed using a deposition process in [0085], Fig. 3) after selectively etching (Ham in [0085], Fig. 3) the metal line opening (10b-O’s Ham in [0085], Fig. 3).
Re: Claim 7, Sakamoto modified by Ham, Tour and Zhang discloses the method of claim 4, where applying the laser light source (Tour applied to Ham and Sakamoto) comprises: applying a laser irradiation source (Tour applied to Ham and Sakamoto) to the polyimide (Tour applied to Ham and Sakamoto) located in the via opening (10a-O’s Ham in [0085], Fig. 3) to form a graphene via structure (40a’s Ham in [0085], Fig. 3) in the first dielectric layer (10a,b’s Ham in [0085], Fig. 3) in direct electrical contact with the first conductive contact layer (30-40’s Ham in [0085], Fig. 3); and applying a laser irradiation source (Tour applied to Ham and Sakamoto) to the polyimide (Tour applied to Ham and Sakamoto) located in the metal line opening (10b-O’s Ham in [0085], Fig. 3) to form a graphene wiring line structure (40b’s Ham in [0085], Fig. 3) in the first dielectric layer (10a,b’s Ham in [0085], Fig. 3) which is in direct electrical contact with the graphene via structure (40a’s Ham in [0085], Fig. 3).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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