DETAILED ACTION
This office action is in response to the election filed 1/18/2026.
Currently, claims 1-20 are pending, of which claims 19-20 have been withdrawn from consideration.
Election/Restrictions
Applicant’s election without traverse of claims 1-18 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9-15 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harada (US 2010/0033407).
Pertaining to claims 1 and 10, Harada shows, with reference to FIG. 4, a display panel, comprising:
an array substrate, comprising:
a substrate (61);
a source electrode (64) and a drain electrode (65) disposed on the substrate, wherein the drain electrode is disposed at one side of the source electrode;
a semiconductor layer (66) disposed between the source electrode and the drain electrode, wherein the semiconductor layer overlaps with a portion of the source electrode and a portion of the drain electrode; and
a channel defining layer (67), wherein the channel defining layer is correspondingly disposed on the source electrode and the drain electrode, and is disposed around the semiconductor layer.
Pertaining to claims 2 and 11, Harada shows the film thickness of the channel defining layer is greater than or equal to the film thickness of the semiconductor layer (FIG. 4).
Pertaining to claims 3 and 12, Harada shows the channel defining layer is provided with a printing opening, the semiconductor layer is correspondingly disposed in the printing opening (para. [0048]) and is in contact with the source electrode and the drain electrode which are corresponding to the printing opening (FIG. 4), and the semiconductor layer is in contact with an inner sidewall of the channel defining layer (FIG. 4).
Pertaining to claims 4 and 13, Harada shows the source electrode and the drain electrode are correspondingly disposed at two sides of the printing opening, and a portion of the source electrode and a portion of the drain electrode extend into the printing opening (FIG. 4).
Pertaining to claims 5 and 14, Harada shows each of the source electrode and the drain electrode comprises an extension portion, the extension portion of the source electrode and the extension portion of the drain electrode both extend into the printing opening, and at least a portion of the semiconductor layer overlaps with/covers the extension portion of the source electrode and the extension portion of the drain electrode (FIG. 4).
Pertaining to claims 6 and 15, Harada shows the length of the extension portion of the source electrode is the same as the length of the extension portion of the drain electrode, and an overlapping area between the semiconductor layer and the extension portion of the source electrode is the same as an overlapping area between the semiconductor layer and the extension portion of the drain electrode (FIG. 4).
Pertaining to claims 9 and 18, Harada shows the semiconductor layer comprises an organic semiconductor layer (para. [0052]).
Claims 1-2, 8-11 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishihara et al. (US 2002/0012080).
Pertaining to claims 1 and 10, Ishihara shows, with reference to FIG. 1, a display panel, comprising:
an array substrate, comprising:
a substrate (101);
a source electrode (104) and a drain electrode (105) disposed on the substrate, wherein the drain electrode is disposed at one side of the source electrode;
a semiconductor layer (107) disposed between the source electrode and the drain electrode, wherein the semiconductor layer overlaps with a portion of the source electrode and a portion of the drain electrode; and
a channel defining layer (106), wherein the channel defining layer is correspondingly disposed on the source electrode and the drain electrode, and is disposed around the semiconductor layer.
Pertaining to claims 2 and 11, Ishihara shows the film thickness of the channel defining layer is greater than or equal to the film thickness of the semiconductor layer (FIG. 1(A)).
Pertaining to claims 8 and 17, Ishihara shows the width of the source electrode and the width of the drain electrode are less than the width of the semiconductor layer (FIG. 1(B)).
Pertaining to claims 9 and 18, Ishihara shows the semiconductor layer comprises an organic semiconductor layer (para. [0036]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Harada.
Although Harada does not explicitly show the extension portions have a length greater than or equal to 2.5 millimeters, this is not a patentably distinguishable feature. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). The extension portion length determines the contact area between the source/drain and channel, and thus impacts transistor performance.
Note that the specification contains no disclosure of either the critical nature of the claimed dimensions or of any unexpected results arising there from. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in the claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1515, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chuman et al. (US 2010/0090204) discloses a device utilizing a channel defining layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896
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