Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment, received 2/23/2026, has been entered.
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aoki et al. (US Pub. No. 2014/0367770 A1), hereafter referred to as Aoki.
As to claim 1, Aoki discloses a transistor (fig 1, [0051]) comprising:
a first drain region (fig 1, upper middle region D);
a first source region (left side source region S) disposed on a first side of the first drain region (left side of D), a first active region (channel region below gate finger 5) defined between the first drain region (D) and the first source region (S);
a second source region (S on the right side) disposed on a second side of the first drain region (right side of D) opposite the first side (left side of D) and displaced in a widthwise direction from the first source region (see annotated figure 1, below, with dotted lines for first source region and second source region), a second active region (region below gate finger on right side) defined between the first drain region (middle drain region D) and the second source region (source region on the left);
a first gate electrode finger disposed over the first active region (gate finger 5 between S/D on left), the first gate electrode finger and the first source region having equal widths (see annotated fig 1 below); and
a second gate electrode finger disposed over the second active region (gate finger 5 between S/D on right).
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As to claim 2, Aoki discloses the transistor of claim 1 (paragraphs above),
a second drain region (fig 1, drain region to the right of the right side source S) on a side of the second source region opposite the first drain region (drain region to the right of S on the right side), the second drain region aligned widthwise with the first drain region (top of the first and top of the second drain regions are aligned widthwise), a third active region formed between the second drain region and the second source region (region of gate finger 5 between the S/D).
As to claim 3, Aoki discloses the transistor of claim 2 (paragraphs above).
a third source region on a side of the second drain region opposite the second source region (refer to figure 30 and correspond each elements of claims 1-2 in the same manner with figure 30; additionally, figure 30 shows a third source region to the right of a right side drain region D), the third source region aligned widthwise with the first source region (bottom side of the third source S and the first source region S are aligned widthwise) and displaced widthwise from the second source region (upper and lower widthwise of second source region S), a fourth active region formed between the third source region and second drain region (gate finger 5 between S/D).
As to claim 4, Aoki discloses the transistor of claim 3 (paragraphs above).
wherein each of the first source region, the second source region, and the third source region have same widths (fig 30, Examiner defines the regions of each of the source regions S are considered to be the first through third sources with the same width).
As to claim 5, Aoki discloses the transistor of claim 4 (paragraphs above).
wherein the first active region, the second active region, the third active region, and the fourth active region have same widths (fig 30, each defined active regions, first through fourth, have the same width).
As to claim 6, Aoki discloses the transistor of claim 5 (paragraphs above).
wherein the first active region is displaced widthwise from the second active region (fig 30, first and third are displaced widthwise from each other).
As to claim 7, Aoki discloses the transistor of claim 6 (paragraphs above).
wherein the third active region is aligned widthwise with the first active region (fig 30, part of third active region, defined by gate finger 5, is aligned with adjacent active region defined as the first active region).
As to claim 8, Aoki discloses the transistor of claim 3 (paragraphs above).
wherein the first drain region has a same width as the second drain region (region of drain D considered to be the first and second drain regions D have the same width).
As to claim 9, Aoki discloses the transistor of claim 8 (paragraphs above).
wherein the first drain region includes a first widthwise extension on a second side of the first drain region opposite the first side of the first drain region (fig 30, see regions of drain D), the first widthwise extension having a smaller length than the length of a remainder of the first drain region (regions defined by first region and first widthwise extension of D).
As to claim 10, Aoki discloses the transistor of claim 9 (paragraphs above).
wherein the second drain region includes a second widthwise extension on a same side of the second drain region as the second source region, the second widthwise extension having a smaller length than the length of a remainder of the second drain region (drain region D with second region widthwise extension).
As to claim 11, Aoki discloses the transistor of claim 10 (paragraphs above).
wherein the first drain region and the second drain region are symmetric about the second source region (first and second drain regions D).
As to claim 12, Aoki discloses the transistor of claim 3 (paragraphs above).
a first drain bond pad (3b) disposed at a position displaced in a widthwise direction from the first source region (S) and at least partially aligned in a lengthwise direction with the first source region (source region of S).
As to claim 13, Aoki discloses the transistor of claim 12 (paragraphs above).
a second drain bond pad (3d) disposed at a position displaced in a widthwise direction from the third source region (region S) and at least partially aligned in a lengthwise direction with the third source region (lengthwise direction of S).
As to claim 14, Aoki discloses the transistor of claim 13 (paragraphs above).
a drain tie (fig 2, mounting interconnect 202a-b and interconnect 205) electrically connecting the first drain bond pad to the second drain bond pad (drain pads 3), the drain tie (202a-b and interconnect 205) at least partially aligned in a lengthwise direction with the second source region (S).
As to claim 15, Aoki discloses the transistor of claim 13 (paragraphs above).
wherein a portion of the second source region is disposed between the first drain bond pad and the second drain bond pad (source S between drain bond pads 3b and 3d).
As to claim 16, Aoki discloses the transistor of claim 15 (paragraphs above).
wherein portions of the second active region and third active region are disposed between portions of the first drain bond pad and second drain bond pad (active regions defined by the gate finger 5 between S/D are between 3b and 3d).
As to claim 17, Aoki discloses the transistor of claim 3 (paragraphs above).
a first gate bond pad (4) at least partially aligned in a widthwise direction with the second source region (S).
As to claim 18, Aoki discloses the transistor of claim 17 (paragraphs above).
wherein the first gate bond pad (4) is disposed at least partially between portions of the first source region and the third source region (first and second regions S).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aoki in view of Kobayashi (US Pub. No. 2008/0265314 A1).
As to claim 19, Aoki discloses the transistor of claim 17 (paragraphs above).
Aoki does not disclose a second gate bond pad on an opposite side of the first source region from the first gate bond pad, the first gate bond pad and second gate bond pad being electrically connected to one another.
Nonetheless, Kobayashi discloses a transistor including a first gate bond pad and a second gate bond pad on an opposite side of a first source region from the first gate bond pad (fig 10, left side and right side gate pads 4 with source region S), the first gate bond pad (G on left) and second gate bond pad (G on the right) being electrically connected to one another (through 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a second gate bond pad in the transistor of Aoki as taught by Kobayashi since this will improve the uniformity of the voltage potential at regions of the active area.
As to claim 20, Aoki in view of Kobayashi disclose the transistor of claim 19 (paragraphs above).
Kobayashi further discloses wherein portions of the first active region are disposed between portions of the first gate bond pad and the second gate bond pad (fig 10, portions of active regions between s/d between first and second gate bond pads 4).
Response to Arguments
Applicant's arguments filed 2/23/2026 have been fully considered but they are not persuasive.
Applicant argued that the gate interconnect 5 of Aoki circumscribes the entire area of the transistor of Aoki that the Examiner equates with the recited first source region.
Examiner disagrees because the entire gate interconnect 5 of Aoki is not considered to be a singular gate finger, instead, the portion of the gate interconnection 5 pointed to in the annotated figure, above, is considered to be the gate finger. Claim 1 requires a transistor comprise a first and second gate finger. Figure 1 of Aoki shows a transistor with the source regions and gate fingers as recited in the claims, as detailed in the office action above.
Applicant argued that Kobayashi fails to cure the deficiency of Aoki.
Examiner disagrees because Aoki, as detailed above, does not have a deficiency.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2017/0053938 A1; and US Pub. No. 2018/0374939A1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 3/3/2026