DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment/Restriction
Applicant’s election without traverse of Species I, FIG. 3A, and Claims 1-4, 6, 8-11, and 14-20 in the reply filed on May 18, 2026 is acknowledged. Thus, Claims 5, 7, and 12-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on May 18, 2026.
Specification
The title of the invention is broad and not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 18, the limitation “a shield conductive pattern including line portions” is already recited in claim 17. It is not clear whether they refer to the same element in view of “further comprising”. Thus, the limitation render the claim indefinite and clarification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-11, and 14-20 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2015/0255466 A1 to Hwang et al. (“Hwang”). As to claim 1, Hwang discloses a semiconductor memory device, comprising: a substrate (101); a bit line (109) disposed on the substrate (101) and extending in a first direction parallel to a top surface of the substrate (101); a first word line (106 in 102) extending in a second direction to cross the bit line (109), the second direction parallel to the top surface of the substrate (101) and crossing the first direction; a second word line (106 in 102) extending in the second direction to cross the bit line (109); a back-gate electrode (106 in 104) disposed between the first word line (106 in 102) and the second word line (106 in 102) and extending in the second direction; a first active pattern (124, 125) disposed between the first word line (106 in 102) and the back-gate electrode (106 in 104) and connected to the bit line (109); a second active pattern (124, 125) disposed between the second word line (106 in 102) and the back-gate electrode (106 in 104) and connected to the bit line (109); contact patterns (121) coupled to the first and second active patterns (124, 125), respectively; a first back-gate capping pattern (SP under 121) between the contact patterns (121) and a top surface of the back-gate electrode (106 in 104); and first gate capping patterns (SP2 under 122) between the contact patterns (121) and top surfaces of the first and second word lines (106 in 102), wherein: the first back-gate capping pattern (SP2 under 121) has a first seam (116 under 121) that is formed therein and that extends in the second direction, each of the first gate capping patterns (SP2 under 122) has a second seam (116 under 122) that is formed therein and extends in the second direction, and the first seam (116 under 121) and the second seam (116 under 122) are located at different vertical levels (See Fig. 2, ¶ 0022-¶ 0034) (Notes: the second seam is capped by 122 to be at a lower vertical level. Further, the disclosed word lines and back-gate electrodes are conductive layers adjacent each other with active patterns interposing therebetween). As to claim 2, Hwang further discloses wherein the first seam (116 under 121) of the first back-gate capping pattern (SP under 121) is vertically spaced apart from the contact patterns (121) and is adjacent to the top surface of the back-gate electrode (106 in 104) (See Fig. 2).
As to claim 3, Hwang further discloses wherein the second seams (116 under 122) of the first gate capping patterns (SP2 under 122) are vertically spaced apart from the top surfaces of the first and second word lines (106 in 102) and are adjacent to the contact patterns (121) (See Fig. 2).
As to claim 4, Hwang further discloses wherein the top surfaces of the first and second word lines (106 in 102) are located at substantially the same vertical level as the top surface of the back-gate electrode (106 in 104) (See Fig. 2).
As to claim 8, Hwang discloses further comprising: a peripheral active pattern (201) provided on a peripheral circuit region (200) of the substrate (101), the peripheral active pattern (201) having a first surface and a second surface, which are opposite to each other; and a peripheral transistor (FET) integrated on the first surface of the peripheral active pattern (201), wherein; the first and second active patterns (125) each have a first surface adjacent to the contact patterns (121), and a second surface adjacent to the bit line (109), and the second surface of the peripheral active pattern (201) is located at substantially the same vertical level as the second surfaces of the first and second active patterns (125) (See Fig. 2).
As to claim 9, Hwang discloses a semiconductor memory device, comprising: a substrate (101); a bit line (109) provided on the substrate (101) and extending in a first direction; first active patterns (124, 125) and second active patterns (124, 125) alternately disposed in the first direction on the bit line (109), the first direction parallel to a top surface of the substrate (101); a back-gate electrode (106 in 104) disposed between adjacent ones of the first and second active patterns (124, 125) and extending in a second direction to cross the bit line (109), the second direction parallel to the top surface of the substrate (101) and perpendicular to the first direction; first word lines (106 in 102) disposed adjacent to first side surfaces of the first active patterns (124, 125) respectively and extending in the second direction; second word lines (106 in 104) disposed adjacent to second side surfaces of the second active patterns (124, 125) respectively and extending in the second direction; contact patterns (121) connected to the first and second active patterns (124, 125), respectively; a first back-gate capping pattern (SP2 under 121) between the contact patterns (121) and the back-gate electrode (106 in 104); first gate capping patterns (SP2 under 122) between the contact patterns (121) and the first word lines (106 in 102) and second word lines (106 in 102); a second back-gate capping pattern (SP1) between the bit line (109) and the back-gate electrode (106 in 104); and second gate capping patterns (SP1) between the bit line (109) and the first word lines (106 in 102) and second word lines (106 in 102), wherein: the first back-gate capping pattern (SP2 under 121) has a first seam (116 under 121) that is formed therein and is adjacent to the back-gate electrode (106 in 104), each of the first gate capping patterns (SP2 under 122) has a second seam (116 under 122) that is formed therein and is adjacent to the contact patterns (121), the first seam (116 under 121) of the first back-gate capping pattern (SP2 under 121) is vertically spaced apart from the contact patterns (121), and the second seams (116 under 122) of the first gate capping patterns (SP2 under 122) are vertically spaced apart from top surfaces of the first word lines (106 in 102) and second word lines (106 in 102) (See Fig. 2, ¶ 0022-¶ 0034) (Notes: the disclosed word lines and back-gate electrodes are conductive layers adjacent each other with active patterns interposing therebetween).
As to claim 10, Hwang discloses further comprising first gate insulating patterns (105) comprising a first set (left/right) disposed between the first active patterns (124, 125) and the back-gate electrode (106 in 104) and a second set (left/right) disposed between the second active patterns (124, 125) and the back-gate electrode (106 in 104), and wherein: the first back-gate capping pattern (SP2 under 121) is disposed between adjacent ones of the first gate insulating patterns (105) (See Fig. 2).
As to claim 11, Hwang discloses further comprising: second gate insulating patterns (105) comprising a first set (left/right) respectively disposed between the first active patterns (124, 125) and the first word lines (106 in 102) and a second set (left right) respectively disposed between the second active patterns (124, 125) and the second word lines (106 in 102); and a separation insulating pattern (102), which is disposed between the first word lines (106 in 102) and second word lines (106 in 102) adjacent to each other in the first direction, wherein the first gate capping patterns (SP2 under 122) are respectively disposed between the separation insulating pattern (102) and the second gate insulating patterns (105) (See Fig. 2).
As to claim 14, Hwang further discloses wherein the first seam (116 under 121) and the second seams (116 under 122) extend in the second direction (See Fig. 2).
As to claim 15, Hwang further discloses wherein, when measured in the first direction, a width of each of the first and second active patterns (124, 125) is smaller than a width of each of the contact patterns (121) (See Fig. 2).
As to claim 16, Hwang discloses further comprising data storage patterns (123) disposed on the contact patterns (121) (See Fig. 2).
As to claim 17, Hwang discloses a semiconductor memory device, comprising: a substrate (101); bit lines (109) disposed on the substrate (101) and extending in a first direction parallel to a top surface of the substrate (101); a shielding conductive pattern (120) including line portions, which are disposed between adjacent ones of the bit lines (109) and extend in the first direction; first active patterns (124, 125) and second active patterns (124, 125) alternately disposed in the first direction, on each of the bit lines (109); contact patterns (121) coupled to the first and second active patterns (124, 125), respectively; back-gate electrodes (106 in 104), which are respectively disposed between adjacent ones of the first and second active patterns (124, 125) and extend in a second direction to cross the bit lines (109), the second direction parallel to the top surface of the substrate (101) and perpendicular to the first direction; first word lines (106 in 102) disposed adjacent to the first active patterns (124, 125) respectively and extending in the second direction; second word lines (124, 125) disposed adjacent to the second active patterns (124, 125) respectively and extending in the second direction; a first back-gate capping pattern (SP2 under 121) between the contact patterns (121) and the back-gate electrodes (106 in 104); first gate capping patterns (SP2 under 122) comprising a first set between the contact patterns (121) and the first word lines (106 in 102) and a second set between the contact patterns (121) and the second word lines (106 in 102); a second back-gate capping pattern (SP1) between the bit lines (109) and the back-gate electrodes (106 in 104); second gate capping patterns (SP2 under 122) comprising a first set between the bit lines (109) and the first word lines (106 in 102) and a second set between the bit lines (109) and the second word lines (106 in 102); contact patterns (121) coupled to the first and second active patterns (124, 125), respectively; and data storage patterns (123) coupled to the contact patterns (121), respectively, wherein: the first back-gate capping pattern (SP2 under 121) has a first seam (116 under 121) that is formed therein and extends in the second direction, each of the first gate capping patterns (SP2 under 122) has a second seam (116 under 122) that is formed therein and extends in the second direction, the first seam (116 under 121) is adjacent to a top surface of the back-gate electrodes (106 in 104), and the second seams (116 under 122) are adjacent to the contact patterns (121) (See Fig. 2, ¶ 0022-¶ 0034) (Notes: shielding conductive portion serves as a physical barrier. Further, the disclosed word lines and back-gate electrodes are conductive layers adjacent each other with active patterns interposing therebetween
As to claim 18, Hwang discloses further comprising: a shielding conductive pattern (120) including line portions that are respectively disposed between adjacent ones of the bit lines (109) and extend in the first direction; and a spacer insulating layer (111) disposed between the shielding conductive pattern (120) and the bit lines (109) (See Fig. 2). As to claim 19, Hwang discloses further comprising gate insulating patterns (105) that comprising a first set (left/right) respectively disposed between the first active patterns (124, 125) and the first word lines (106 in 102) and a second set (left/right) respectively disposed between the second active patterns (124, 125) and the second word lines (106 in 102); and a separation insulating pattern (102) that is disposed between the first word lines (106 in 102) and second word lines (106 in 102) facing each other, wherein the first gate capping patterns (SP2 under 122) and the first back-gate capping pattern (SP2 under 121) include an insulating material (air) different from the separation insulating pattern (102) (See Fig. 2). As to claim 20, Hwang further discloses wherein, when measured in the first direction, a width of each of the first and second active patterns (124, 125) is less than a width of each of the contact patterns (121) (See Fig. 2).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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