Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species 3 in the reply filed on 1/20/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Applicant’s traversal is an incomplete argument because it fails to "distinctly and specifically point out the supposed errors" in the Examiner’s finding of mutually exclusive characteristics (37 CFR 1.143).
The Applicant argues that Species 3 is "useable together with" the other species. However, the species remain independent and distinct based on the following physical structural differences:
Substrate Presence (Species 1 & 2 vs. Species 3): Species 1 and 2 are defined by the absence of a second substrate. Species 3 is defined by the presence of a second substrate (700). An embodiment cannot simultaneously lack and possess the same substrate; therefore, they are structurally mutually exclusive.
Active Pattern Geometry (Species 4 vs. Species 1-3): Species 4 requires a "second active pattern 103" with a "different orientation and pattern" compared to the others. The Applicant’s argument of compatibility does not address how a change in geometric orientation constitutes the "same invention" or an "obvious variant."
The argument fails to address the patentable distinctness. The argument that species are "useable together" addresses utility or compatibility, but it does not address patentable distinctness. Two components can be used in the same device yet still represent independent inventions requiring separate searches.
Since the Applicant has not provided evidence that the "no substrate" version is an obvious variant of the "second substrate" version, nor addressed the unique orientation of Species 4, the finding that these species are independent or distinct stands.
The Examiner previously stated that "No single claim is understood generic to all of the disclosed patentably distinct species."
The Applicant’s response failed to identify and/or clarify if any claim is generic. Without a generic claim to bridge the mutually exclusive features of Species 1-4, the Examiner must maintain the restriction to ensure a proper and focused search of the elected invention.
Because the Applicant’s traversal is an incomplete argument that fails to overcome the of mutually exclusive characteristics identified in the restriction, the restriction is maintained and made final.
Species 3 (FIG. 38) is the elected invention. Claims 1-19 and 22, which correspond to Species 3, will be examined on their merits. Claims directed to the non-elected invention: Species 1, 2, and 4 are withdrawn from consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-19 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour et al. (US 20210408018 A1) in view of Chen et al. (US 20240040800 A1)
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CLAIM 1. Haratipour et al. teaches a semiconductor device comprising:
a gate structure 703B on a first substrate 702;
a bit line structure 712+724 on the gate structure;
a contact plug structure 714+118 on the first substrate, the contact plug being spaced apart from the bit line structure 712+724 (Fig. 7 – Plugs are spaced apart as shown in fig. 7, as the identified plugs are over respective S/D regions of the transistor which are spaced, for example, by a channel/gate region.);
a stack structure 100A on the bit line structure and the contact plug structure (Fig. 7), the stack structure 100A including insulation layers 112 and plate electrodes 108+110 alternately stacked in a vertical direction substantially perpendicular to an upper surface of the first substrate (As depicted in fig. 7 Y-axis direction); and
a capacitor (110, 104A and 104B) including:
a second electrode 102 extending through the stack structure 100A and contacting the contact plug structure (¶[0061] – “The electrode 102 is further coupled with a conductive interconnect 118.”);
a ferroelectric pattern 104A+104B ( ¶[0061] – “with ferroelectric layer 104”) on a sidewall of the second electrode102 (Fig. 7).
Haratipour is silent upon first electrodes on a sidewall of the ferroelectric pattern, the first electrodes contacting sidewalls of the plate electrodes, respectively, and being spaced apart from each other in the vertical direction. However, this limitation does not provide a patentable distinction over the prior art under the Broadest Reasonable Interpretation (BRI). Under the guidance of MPEP § 2144.04 (V)(C), the distinction between making a part "separable" or "integral" is a matter of design choice. In the stack structure 100A of Haratipour (Fig. 7), the portion of the plate electrode (110, 108) contacting the ferroelectric material (104B) may be considered a "sidewall electrode region." Whether this sidewall electrode region is integrally formed as the face of the bulk plate electrode or provided as a separable layer is a well-recognized design choice for a PHOSITA.
In the scenario of making the part separable, the "first electrode" may be a conductive barrier layer contacting the ferroelectric material. Chen et al. teaches that ferroelectric capacitors for FeRAM may include conductive barrier layers (also referred to as an "interfacial layer," "intermixing layer," or "diffusion barrier layer") positioned between the electrodes and the ferroelectric material (Chen ¶[0030]1). According to Chen, this barrier material comprises "titanium nitride, platinum, aluminum copper, gold, titanium, tantalum, tantalum nitride, tungsten, tungsten nitride, the like, or any combination" (Chen ¶ [0057]).
It would have been obvious to a PHOSITA at the time of the invention to modify the device of Haratipour to include a conductive barrier layer between the electrode and ferroelectric material, as taught by Chen, to prevent diffusion or intermixing. This modification would result in the structure of Haratipour further comprising first electrodes (i.e., the barrier layer of Chen ¶ [0030]) on a sidewall of the ferroelectric pattern 104. Furthermore, these first electrodes would be contacting sidewalls of the plate electrodes (110, 108), respectively. Because the barrier layers would be disposed at the interface of each distinct plate level in Haratipour's vertical stack, the resulting first electrodes would inherently be spaced apart from each other in the vertical direction (Haratipour Fig. 7). A PHOSITA would have a reasonable expectation of success in this combination because the use of barrier layers to prevent material degradation is a predictable improvement in the field of semiconductor memory.
CLAIM 2. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 1, wherein the second electrode102 has a pillar shape extending in the vertical direction, and wherein the ferroelectric pattern has a cylindrical shape 104 surrounding the sidewall of the second electrode (Haratipour Fig. 7).
CLAIM 3. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 2, wherein each of the first electrodes protrudes from the sidewall of the ferroelectric pattern in a horizontal direction substantially parallel to the upper surface of the first substrate (Haratipour Fig. 7 as modified by Chen et al. – Note the plate electrodes analogously protrude as claimed.).
CLAIM 4. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 1, wherein each of the first electrodes does not contact sidewalls of the insulation layers (Haratipour Fig. 7 as modified by Chen et al. – Chen demonstrates only placing the barrier material at the contact interface.).
CLAIM 5. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 1, wherein each of the first electrodes has a sidewall having a convex shape toward the sidewall of a corresponding one of the plate electrodes in a horizontal direction substantially parallel to the upper surface of the first substrate (Haratipour Fig. 7 as modified by Chen et al. – This is the understood cylindrical shape.).
CLAIM 7. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 1, wherein the capacitor is one of a plurality of capacitors spaced apart from each other in first and second directions that are substantially parallel to the upper surface of the first substrate and cross each other, and the plurality of capacitors extend through the stack structure (Haratipour Fig. 7).
CLAIM 8. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 1, wherein:
the gate structure 703Bextends in a first direction substantially parallel to the upper surface of the first substrate 702 (e.g. Y axis direction Fig. 7), and is one of a plurality of gate structures spaced apart from each other in a second direction that is substantially parallel to the upper surface of the first substrate and intersects the first direction, and the stack structure is one of a plurality of stack structures being spaced apart from each other in the second direction, each of the plurality of stack structures extending in the first direction (Haratipour Fig. 7 & ¶46- the device is a memory array, thus implicitly a plurality of spaced apart devise making up the array.).
CLAIM 9. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 8, wherein the capacitor is one of a plurality of capacitors spaced apart from each other in the first direction, and each of the plurality of capacitors extends through a corresponding one of the plurality of stack structures (Haratipour Fig. 7 & ¶46- the device is a memory array, thus implicitly a plurality of spaced apart devise making up the array.).
CLAIM 10. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 1, wherein: the gate structure extends in a first direction substantially parallel to the upper surface of the first substrate, and an edge portion of the stack structure in the first direction has a staircase shape (Haratipour Fig. 7 & ¶60- also refers to the shape as a “staircase”.).
CLAIM 11. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 1, further comprising: a second substrate under the first substrate; and a lower circuit pattern between the second substrate and the first substrate(Haratipour Fig. 7 & ¶173- While Haratipour may not explicitly state a “second substrate”, the substate is described as optionally being a SOI which is a “Silicon On Insulator”. This structure by design under BRI has a second substrate. The first substrate is the thin Si layer where the active devices are formed, and the underlying Insulator or carrier would be considered second or additional substrates. As such, a second substrate, is inferred with the SOI option taught in Haratipour.).
CLAIM 12. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 11, wherein the first substrate includes polysilicon (Haratipour ¶[0172] – “ In an embodiment, the underlying substrate 702 represents a surface used to manufacture integrated circuits. Suitable substrate 702 includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), “)
CLAIM 13. Haratipour et al. in view of Chen et al. teaches a semiconductor device comprising:
a gate structure on a first substrate 703B, the gate structure extending in a first direction substantially parallel to an upper surface of the first substrate (As depicted in Haratipour Fig. 7 Y-axis direction);
a bit line structure 712+724 on the gate structure703B;
a contact plug structure 714+118 on the first substrate 702, the contact plug being spaced apart from the bit line structure 712+724 (Fig. 7 – Plugs are spaced apart as shown in fig. 7, as the identified plugs are over respective S/D regions of the transistor which are spaced, for example, by a channel/gate region.);
a stack structure 100A on the bit line structure and the contact plug structure, the stack structure including insulation layers and plate electrodes 108+110 alternately stacked in a vertical direction substantially perpendicular to an upper surface of the first substrate(As depicted in Haratipour Fig. 7 Y-axis direction); and
a capacitor (110, 104A and 104B) including: a second electrode 102 extending through the stack structure and contacting the contact plug structure (¶[0061] – “The electrode 102 is further coupled with a conductive interconnect 118.”);
a ferroelectric pattern 104A+104B ( ¶[0061] – “with ferroelectric layer 104”) on a sidewall of the second electrode 102 (Fig. 7), and a first electrode on a sidewall of the ferroelectric pattern, the first electrode (i.e. a barrier layer between the plate electrode and ferroelectric material will constitute a first electrode, as described in Chen et al. See regarding claim 1 or below for motivation for the combination.) contacting a sidewall of each of the plate electrodes, wherein an edge portion of the stack structure in the first direction has a staircase shape (Haratipour Fig. 7 & ¶60- also refers to the shape as a “staircase”.).
Haratipour is silent upon first electrodes on a sidewall of the ferroelectric pattern, the first electrodes contacting sidewalls of the plate electrodes, respectively, and being spaced apart from each other in the vertical direction. However, this limitation does not provide a patentable distinction over the prior art under the Broadest Reasonable Interpretation (BRI). Under the guidance of MPEP § 2144.04 (V)(C), the distinction between making a part "separable" or "integral" is a matter of design choice. In the stack structure 100A of Haratipour (Fig. 7), the portion of the plate electrode (110, 108) contacting the ferroelectric material (104B) may be considered a "sidewall electrode region." Whether this sidewall electrode region is integrally formed as the face of the bulk plate electrode or provided as a separable layer is a well-recognized design choice for a PHOSITA.
In the scenario of making the part separable, the "first electrode" may be a conductive barrier layer contacting the ferroelectric material. Chen et al. teaches that ferroelectric capacitors for FeRAM may include conductive barrier layers (also referred to as an "interfacial layer," "intermixing layer," or "diffusion barrier layer") positioned between the electrodes and the ferroelectric material (Chen ¶[0030]2). According to Chen, this barrier material comprises "titanium nitride, platinum, aluminum copper, gold, titanium, tantalum, tantalum nitride, tungsten, tungsten nitride, the like, or any combination" (Chen ¶ [0057]).
It would have been obvious to a PHOSITA at the time of the invention to modify the device of Haratipour to include a conductive barrier layer between the electrode and ferroelectric material, as taught by Chen, to prevent diffusion or intermixing. This modification would result in the structure of Haratipour further comprising first electrodes (i.e., the barrier layer of Chen ¶ [0030]) on a sidewall of the ferroelectric pattern 104. Furthermore, these first electrodes would be contacting sidewalls of the plate electrodes (110, 108), respectively. Because the barrier layers would be disposed at the interface of each distinct plate level in Haratipour's vertical stack, the resulting first electrodes would inherently be spaced apart from each other in the vertical direction (Haratipour Fig. 7). A PHOSITA would have a reasonable expectation of success in this combination because the use of barrier layers to prevent material degradation is a predictable improvement in the field of semiconductor memory.
CLAIM 14. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 13, wherein the capacitor is one of a plurality of capacitors spaced apart from each other in the first direction (Haratipour, Fig. 7 x-axis) and a second direction (Haratipour, Fig. 7 – z-axis), which is substantially parallel to the upper surface of the first substrate and intersects the first direction, and the plurality of capacitors extending through the stack structure (Haratipour Fig. 7 & ¶46- the device is a memory array, thus implicitly a plurality of spaced apart devise making up the array.).
CLAIM 15. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 13, wherein: the gate 703B structure is one of a plurality of gate structures spaced apart from each other in a second direction substantially parallel to the upper surface of the first substrate and intersecting the first direction, and the stack structure is one of a plurality of stack structures spaced apart from each other in the second direction, each of the plurality of stack structures extending in the first direction (Haratipour Fig. 7 & ¶46- the device is a memory array, thus implicitly a plurality of spaced apart devise making up the array.).
CLAIM 16. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 15, wherein the capacitor is one of a plurality of capacitors spaced apart from each other in the first direction, and each of the plurality of capacitors extends through a corresponding one of the plurality of stack structures (Haratipour Fig. 7 & ¶46- the device is a memory array, thus implicitly a plurality of spaced apart devise making up the array.).
CLAIM 17. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 13, wherein: the second electrode 102 has a pillar shape extending in the vertical direction, and the ferroelectric pattern has a cylindrical shape surrounding the sidewall of the second electrode (Haratipour Fig. 7).
CLAIM 18. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 17, wherein the first electrode protrudes from the sidewall of the ferroelectric pattern in a horizontal direction substantially parallel to the upper surface of the first substrate (Haratipour Fig. 7 as modified by Chen et al. – Note the plate electrodes analogously protrude as claimed.).
CLAIM 19. Haratipour et al. in view of Chen et al. teaches a semiconductor device as claimed in claim 13, wherein the first electrode does not contact sidewalls of the insulation layers (Haratipour Fig. 7 as modified by Chen).
CLAIM 22. Haratipour et al. in view of Chen et al. teaches a semiconductor device comprising: active patterns on a first substrate (transistor 703/704/706) ; an isolation structure 708 on the first substrate 702, the isolation structure covering sidewalls of the active patterns 704/706; gate 703B structures extending through upper portions of the active patterns and the isolation structure, each of the gate 703B structures extending in a first direction (y-axis) substantially parallel to an upper surface of the first substrate 702, and the gate structures 703B being spaced apart from each other in a second direction, which is substantially parallel to the upper surface of the first substrate and intersects the first direction (Haratipour Fig. 7 & ¶46- the device is a memory array, thus implicitly a plurality of spaced apart devise making up the array.).
bit line structures 712+724 on the active patterns 704 and the isolation structure 708, each of the bit line structures extending in the second direction (y-axis), and the bit line structures being spaced apart from each other in the first direction (Haratipour Fig. 7); contact plug structures 712/714/724/726/118 contacting upper surfaces of the active patterns, respectively (Haratipour Fig. 7);
a stack structure 100A on the bit line structures and the contact plug structures, the stack structure including insulation layers 112 and plate electrodes 110+108 alternately stacked in a vertical direction substantially perpendicular to the upper surface of the first substrate (Haratipour Fig. 7); and
a capacitor (110, 104A and 104B) including:
a second electrode 102 extending through the stack structure and contacting each of the contact plug structures (Haratipour Fig. 7);
a ferroelectric pattern 104 on a sidewall of the second electrode 102;
and first electrodes (E.g. Barrier layers are analogous to the claimed first electrodes. See Haratipour as modified by Chen regarding claim 1 or below.) on sidewalls of the ferroelectric pattern, the first electrodes contacting sidewalls of the plate electrodes, respectively, and being spaced apart from each other in the vertical direction (Haratipour Fig. 7).
Haratipour is silent upon first electrodes on a sidewall of the ferroelectric pattern, the first electrodes contacting sidewalls of the plate electrodes, respectively, and being spaced apart from each other in the vertical direction. However, this limitation does not provide a patentable distinction over the prior art under the Broadest Reasonable Interpretation (BRI). Under the guidance of MPEP § 2144.04 (V)(C), the distinction between making a part "separable" or "integral" is a matter of design choice. In the stack structure 100A of Haratipour (Fig. 7), the portion of the plate electrode (110, 108) contacting the ferroelectric material (104B) may be considered a "sidewall electrode region." Whether this sidewall electrode region is integrally formed as the face of the bulk plate electrode or provided as a separable layer is a well-recognized design choice for a PHOSITA.
In the scenario of making the part separable, the "first electrode" may be a conductive barrier layer contacting the ferroelectric material. Chen et al. teaches that ferroelectric capacitors for FeRAM may include conductive barrier layers (also referred to as an "interfacial layer," "intermixing layer," or "diffusion barrier layer") positioned between the electrodes and the ferroelectric material (Chen ¶[0030]3). According to Chen, this barrier material comprises "titanium nitride, platinum, aluminum copper, gold, titanium, tantalum, tantalum nitride, tungsten, tungsten nitride, the like, or any combination" (Chen ¶ [0057]).
It would have been obvious to a PHOSITA at the time of the invention to modify the device of Haratipour to include a conductive barrier layer between the electrode and ferroelectric material, as taught by Chen, to prevent diffusion or intermixing. This modification would result in the structure of Haratipour further comprising first electrodes (i.e., the barrier layer of Chen ¶ [0030]) on a sidewall of the ferroelectric pattern 104. Furthermore, these first electrodes would be contacting sidewalls of the plate electrodes (110, 108), respectively. Because the barrier layers would be disposed at the interface of each distinct plate level in Haratipour’s vertical stack, the resulting first electrodes would inherently be spaced apart from each other in the vertical direction (Haratipour Fig. 7). A PHOSITA would have a reasonable expectation of success in this combination because the use of barrier layers to prevent material degradation is a predictable improvement in the field of semiconductor memory.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour et al. (US 20210408018 A1) in view of Chen et al. (US 20240040800 A1) in view of Dutta et al. (US 20240114694 A1).
6. (Original) The semiconductor device as claimed in claim 1, however are silent upon the capability wherein each of the plate electrodes includes polysilicon doped with impurities or silicon-germanium doped with impurities, and each of the first and second electrodes includes a metal. Dutta et al. teaches “The conductive lines, vias and plate lines, as well as the outer and inner electrodes 117 and 121, can be implemented with any suitable conductive materials (e.g., copper, tungsten, molybdenum, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or doped polysilicon). Any of these conductive features may include multi-layer configurations, such as a liner or barrier layer (e.g., titanium nitride liner with tungsten fill).” The conductive lines, vias and plate lines, as well as the outer and inner electrodes 117 and 121, can be implemented with any suitable conductive materials (e.g., copper, tungsten, molybdenum, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or doped polysilicon). Any of these conductive features may include multi-layer configurations, such as a liner or barrier layer (e.g., titanium nitride liner with tungsten fill).(Dutta ¶[0039]).
In view of Dutta ¶39, it would be obvious to a PHOSITA at the time the invention was made to select polysilicon for a plate electrode and subsequent barrier material to be a first electrode, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Conclusion
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
2/13/2026
/JARRETT J STARK/ Primary Examiner, Art Unit 2898
1 Chen et al. – [0030] With reference to FIG. 1, a cross-sectional view 100 of some embodiments of a memory cell 102 is provided in which a blocking layer 104 is configured to block diffusion of metal from a top electrode 106 to a ferroelectric layer 108. In some embodiments, the blocking layer 104 may additionally or alternatively be referred to as an interfacial layer, an intermixing layer, a diffusion barrier layer, the like, or any combination of the foregoing. The memory cell 102 may, for example, be or comprise a metal-ferroelectric-metal (MFM) cell, a ferroelectric capacitor, a ferroelectric tunnel junction (FTJ), the like, or any combination of the foregoing.
2 Chen et al. – [0030] With reference to FIG. 1, a cross-sectional view 100 of some embodiments of a memory cell 102 is provided in which a blocking layer 104 is configured to block diffusion of metal from a top electrode 106 to a ferroelectric layer 108. In some embodiments, the blocking layer 104 may additionally or alternatively be referred to as an interfacial layer, an intermixing layer, a diffusion barrier layer, the like, or any combination of the foregoing. The memory cell 102 may, for example, be or comprise a metal-ferroelectric-metal (MFM) cell, a ferroelectric capacitor, a ferroelectric tunnel junction (FTJ), the like, or any combination of the foregoing.
3 Chen et al. – [0030] With reference to FIG. 1, a cross-sectional view 100 of some embodiments of a memory cell 102 is provided in which a blocking layer 104 is configured to block diffusion of metal from a top electrode 106 to a ferroelectric layer 108. In some embodiments, the blocking layer 104 may additionally or alternatively be referred to as an interfacial layer, an intermixing layer, a diffusion barrier layer, the like, or any combination of the foregoing. The memory cell 102 may, for example, be or comprise a metal-ferroelectric-metal (MFM) cell, a ferroelectric capacitor, a ferroelectric tunnel junction (FTJ), the like, or any combination of the foregoing.