Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment, received 3/23/2026, has been entered.
Claims 1-7 and 16-28 are presented for examination.
Claim Rejections - 35 USC § 112
Claims 23-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 23 recites the limitation "The semiconductor device" in line 1. There is insufficient antecedent basis for this limitation in the claim. Claims 24-28 are indefinite because of their dependence from claim 23.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US Pub. No. 2021/0375722 A1), hereafter referred to as Kim.
As to claim 1, Kim discloses a semiconductor device (offset contact embodiment shown in fig 9 structure 100C’ including structural details pointed to in fig 7, 100C; [0087]), comprising:
a substrate (101) comprising an active pattern (105);
a source/drain pattern (110) on the active pattern (105);
a device isolation layer (162) at a lateral side of the active pattern (105);
a lower power structure (250) below a top surface of the substrate (101);
an insulating layer (131) on the top surface of the substrate (101);
a lower contact (120) penetrating the device isolation layer (162) and connecting the source/drain pattern (110) to the lower power structure (250); and
a power delivery network layer (ML2) below the top surface of the substrate (101),
wherein the lower power structure (250) comprises a connecting portion (250) connected to the lower contact (120),
wherein the lower contact (120) comprises a protruding portion buried in the connecting portion (portion of 120 protruding into and buried in connecting portion 250),
wherein the insulating layer (131) is disposed between the connecting portion (250) and the device isolation layer (162), and
wherein the insulating layer (131) extends on a top surface of the substrate (substrate portion 102) in parallel with the top surface of the substrate (see annotated figure 9 below).
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As to claim 2, Kim discloses the semiconductor device of claim 1 (paragraphs above),
a top surface of the connecting portion (top of 250) is in direct contact with the insulating layer (131).
As to claim 3, Kim discloses the semiconductor device of claim 1 (paragraphs above),
wherein the connecting portion (250) encloses a bottom surface and opposite side surfaces of the protruding portion (bottom and sides of 120).
As to claim 4, Kim discloses the semiconductor device of claim 1 (paragraphs above),
a metal layer (185; [0059]) comprising an interconnection metal line (upper line region of 185), above the source/drain pattern (110),
wherein the lower contact (120) is connected to the source/drain pattern (110) through the interconnection metal line (185).
As to claim 5, Kim discloses the semiconductor device of claim 1 (paragraphs above),
wherein at least a portion of a side surface of the lower contact (120) is in contact with the insulating layer (131).
As to claim 6, Kim discloses the semiconductor device of claim 1 (paragraphs above),
wherein as a distance to a bottom surface of the power delivery network layer decreases, a width of the lower contact decreases (width of 120 decreases towards ML2).
As to claim 7, Kim discloses the semiconductor device of claim 1 (paragraphs above),
wherein the power delivery network layer is configured to apply a power voltage to the lower power structure ([0053]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee et al. (US Pub. No. 2023/0022545 A1), hereafter referred to as Lee.
As to claim 16, Kim discloses a semiconductor device (offset contact embodiment shown in fig 9 structure 100C’ including structural details pointed to in fig 7, 100C; [0087]), comprising:
a substrate (101) comprising an active pattern (105);
a device isolation layer (162) at a lateral side of the active pattern (105);
an insulating layer (131) between the substrate (101) and the device isolation layer (162), the insulating layer (131) extended on and contacting a top surface of the substrate (102, see annotated fig 9 above);
a channel pattern (fig 2, cross-section II-II’; channel region of active fin 105) and a source/drain pattern (110) on the active pattern (105);
a gate electrode (fig 2, cross-section II-II’; 145) on the channel pattern (channel region of 105);
a gate insulating layer (142) between the gate electrode (145) and the channel pattern (channel region of 105);
a gate spacer (141) on a side surface of the gate electrode (145);
a gate capping pattern (147) on a top surface of the gate electrode (145);
an interlayer insulating layer (165) isolating the source/drain pattern (110) and the gate capping pattern (147);
an active contact (180) provided to penetrate the interlayer insulating layer (165), and electrically connected to the source/drain pattern (110);
a metal-semiconductor compound layer ([0059]) between the active contact and the source/drain pattern ([0059]);
a first metal layer (V1) on the interlayer insulating layer (165), the first metal layer comprising an interconnection line (V1) electrically connected to the active contact (180);
a second metal layer (M1) on the first metal layer (V1), the second metal layer comprising a second interconnection line electrically connected to the first metal layer (M1 to V1);
a lower power structure (250) in the substrate (101);
a lower contact (120) extended into the substrate (101), the lower contact (120) connecting the active contact (180) to the lower power structure (250); and
a power delivery network layer (ML2) below the top surface of the substrate (101),
wherein the lower contact (120) comprises a lower portion inserted in the lower power structure (250), and
wherein a top surface of the lower power structure (250) is in a direct contact with the insulating layer (131).
Kim does not disclose a gate contact provided to penetrate the interlayer insulating layer and the gate capping pattern, and electrically connected to the gate electrode.
Nonetheless, Lee discloses a gate contact (fig 14D, GC) provided to penetrate an interlayer insulating layer (120) and a gate capping pattern (GP), and electrically connected to a gate electrode (GE).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to provide a gate contact in the semiconductor device of Kim as taught by Lee since this will allow for voltage control of the gate electrode of the transistor device.
As to claim 17, Kim in view of Lee disclose the semiconductor device of claim 16 (paragraphs above).
Kim further discloses wherein the insulating layer (131) is disposed between the lower power structure (250) and the device isolation layer (162).
As to claim 18, Kim in view of Lee disclose the semiconductor device of claim 16 (paragraphs above).
Kim further discloses a metal layer (180) comprising an interconnection metal line (180A), above the source/drain pattern (110),
wherein the lower contact (120) is connected to the source/drain (110) pattern through the interconnection metal line (180A).
As to claim 19, Kim in view of Lee disclose the semiconductor device of claim 16 (paragraphs above).
Kim further discloses wherein at least a portion of a side surface of the lower contact (120) is in contact with the insulating layer (131).
As to claim 20, Kim in view of Lee disclose the semiconductor device of claim 16 (paragraphs above).
Kim further discloses wherein as a distance to a bottom surface of the substrate decreases, a width of the lower contact decreases (width of 120 decreases towards ML2).
Claim(s) 21 and 23-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Choi et al. (US Pub. No. 2022/0415782 A1), hereafter referred to as Choi.
As to claim 21, Kim discloses the semiconductor device of claim 1 (paragraphs above),
Kim does not disclose wherein the source/drain pattern is in a logic cell, and the lower contact and the lower power structure are in a dummy cell comprising a dummy source/drain pattern on which no contact structure connecting the dummy source/drain pattern to a metal line is disposed.
Nonetheless, Choi discloses wherein the source/drain pattern is in a logic cell, and the lower contact and the lower power structure are in a dummy cell comprising a dummy source/drain pattern on which no contact structure connecting the dummy source/drain pattern to a metal line is disposed (figs 1-3 and [0027]-[0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the dummy logic cell and logic cell of Choi using the semiconductor structure as taught by Kim since this will allow for fast operation speed as well as operational accuracy.
As to claim 23, Kim disclose a semiconductor device (fig, 7), comprising:
a substrate (101) comprising a logic cell region (100C);
a lower power structure (250) buried below a top surface of the substrate (101);
a logic transistor on the logic cell region (transistor shown in fig 7);
a first metal layer on the logic cell transistor, the first metal layer comprising a first interconnection line (M1);
a power delivery network layer (M2) below the substrate (101);
an active contact provided in the logic cell region and electrically connected to the first interconnection line; and
a lower contact (120) electrically connecting the lower power structure (250) and the first interconnection line (M1),
wherein the lower power structure (250) comprises a connecting portion (upper portion) connected to the lower contact (120), and
wherein the lower contact (120) comprises a protruding portion buried in the connecting portion (upper portion of 250).
Kim does not disclose a dummy cell region, a dummy cell transistor on the dummy cell region.
Nonetheless, Nonetheless, Choi discloses a dummy cell region and a dummy cell transistor on the dummy cell region (figs 1-3 and [0027]-[0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the dummy logic cell and logic cell of Choi using the semiconductor structure as taught by Kim since this will allow for fast operation speed as well as operational accuracy.
As to claim 24, Kim in view of Choi disclose the semiconductor device of claim 23 (paragraphs above).
Kim further discloses an insulating layer (131) on the top surface of the substrate (101); and
a device isolation layer (162) on the insulating layer (131),
wherein the insulating layer (131) is between the connecting portion (upper portion of 250) and the device isolation layer (162).
As to claim 25, Kim in view of Choi disclose the semiconductor device of claim 24 (paragraphs above).
Kim further discloses wherein the insulating layer (131) extends on the top surface of the substrate in parallel with the top surface of the substrate (see annotated figure 9 above).
As to claim 26, Kim in view of Choi disclose the semiconductor device of claim 23 (paragraphs above).
Kim further discloses wherein the lower contact (120) vertically extends from the lower power structure (250) toward the first interconnection line (M1).
As to claim 27, Kim in view of Choi disclose the semiconductor device of claim 23 (paragraphs above).
Kim further discloses wherein the power delivery network layer is configured to apply a power voltage to the lower power structure ([0053]).
As to claim 28, Kim in view of Choi disclose the semiconductor device of claim 23 (paragraphs above).
Kim further discloses wherein the connecting portion (upper portion of 250) encloses a bottom surface and opposite side surfaces of the protruding portion (lower portion of 120).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee and further in view of Choi.
As to claim 22, Kim in view of Lee disclose the semiconductor device of claim 16 (paragraphs above).
Kim in view of Lee do not disclose wherein the source/drain pattern is in a logic cell, and the lower contact and the lower power structure are in a dummy cell comprising a dummy source/drain pattern on which no contact structure connecting the dummy source/drain pattern to a metal line is disposed.
Nonetheless, Choi discloses wherein the source/drain pattern is in a logic cell, and the lower contact and the lower power structure are in a dummy cell comprising a dummy source/drain pattern on which no contact structure connecting the dummy source/drain pattern to a metal line is disposed (figs 1-3 and [0027]-[0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the dummy logic cell and logic cell of Choi using the semiconductor structure as taught by Kim since this will allow for fast operation speed as well as operational accuracy.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7 and 16-28 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2022/0271045A1 and US 2022/0208673A1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 4/10/2026
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