Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment, received 6/12/2026, has been entered.
Claims 1-7 and 16-28 are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 23-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. No. 2021/0375722 A1), hereafter referred to as Kim, in view of Choi et al. (US Pub. No. 2022/0415782 A1), hereafter referred to as Choi.
As to claim 23, Kim disclose a semiconductor device (fig, 7), comprising:
a substrate (101) comprising a logic cell region (100C);
a lower power structure (250) buried below a top surface of the substrate (101);
a logic transistor on the logic cell region (transistor shown in fig 7);
a first metal layer on the logic cell transistor (fig 7 transistor), the first metal layer comprising a first interconnection line (M1);
a power delivery network layer (M2) below the substrate (101);
an active contact (V1) provided in the logic cell region (region of fig 7) and electrically connected to the first interconnection line (M1); and
a lower contact (120) electrically connecting the lower power structure (250) and the first interconnection line (M1),
wherein the lower power structure (250) comprises a connecting portion (upper portion) connected to the lower contact (120), and
wherein the lower contact (120) comprises a protruding portion buried in the connecting portion (upper portion of 250).
Kim does not disclose a dummy cell region, a dummy cell transistor on the dummy cell region.
Nonetheless, Nonetheless, Choi discloses a dummy cell region and a dummy cell transistor on the dummy cell region (figs 1-3 and [0027]-[0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the dummy logic cell and logic cell of Choi using the semiconductor structure as taught by Kim since this will allow for fast operation speed as well as operational accuracy.
As to claim 24, Kim in view of Choi disclose the semiconductor device of claim 23 (paragraphs above).
Kim further discloses an insulating layer (131) on the top surface of the substrate (101); and
a device isolation layer (162) on the insulating layer (131),
wherein the insulating layer (131) is between the connecting portion (upper portion of 250) and the device isolation layer (162).
As to claim 25, Kim in view of Choi disclose the semiconductor device of claim 24 (paragraphs above).
Kim further discloses wherein the insulating layer (131) extends on the top surface of the substrate in parallel with the top surface of the substrate (see annotated figure 9 above).
As to claim 26, Kim in view of Choi disclose the semiconductor device of claim 23 (paragraphs above).
Kim further discloses wherein the lower contact (120) vertically extends from the lower power structure (250) toward the first interconnection line (M1).
As to claim 27, Kim in view of Choi disclose the semiconductor device of claim 23 (paragraphs above).
Kim further discloses wherein the power delivery network layer is configured to apply a power voltage to the lower power structure ([0053]).
As to claim 28, Kim in view of Choi disclose the semiconductor device of claim 23 (paragraphs above).
Kim further discloses wherein the connecting portion (upper portion of 250) encloses a bottom surface and opposite side surfaces of the protruding portion (lower portion of 120).
Allowable Subject Matter
Claims 1-7 and 16-22 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Applicant’s arguments on pages 8-10 of the response received 6/12/2026 are persuasive.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7 and 16-22 are persuasive.
Applicant argued that that the Kim reference fail to teach or suggest dummy logic cells as claimed and the Choi reference fails to teach or suggest the lower contact and the lower power structure as claimed, and the Examiner has failed to explain how the combination of Kim and hoi would result in the claimed lower contact and the lower power structure being provided in the claimed dummy cell.
Examiner disagrees because, even though the Examiner agrees that neither Kim nor Choi teach all of the limitations of the claim, the combination does render obvious the claim limitations. Specifically, the combination of Kim with Choi results in the lower contact and the lower power structure being provided similarly in both the logic cell region as well as the dummy logic cell region as is well known in the art.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2022/0271045A1 and US 2022/0208673A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 8/28/2026
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