DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (U.S. Patent No. 8,779,599).
Regarding to claim 1, Lin teaches a semiconductor device comprising:
a first semiconductor chip (Fig. 1A, Fig. 6), the first semiconductor chip comprising:
a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view (Fig. 1A, Fig. 6, element 38, column 2, lines 33-34, the first surface is the bottom surface, the second surface is the top surface);
a first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first active layer (Fig. 6, element 36, column 2, lines 33-34);
a second chip connection pad on the second surface of the first semiconductor substrate and connected to the first through electrode (Fig. 6, element 32, column 2, lines 23-24);
a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a line pattern extending horizontally along the second surface of the first semiconductor substrate (Fig. 1A, Fig. 6, element 30B, column 2, line 5); and
a first chip connection pad on the first surface of the first semiconductor substrate and connected to the first through electrode (Fig. 6, element 54; column 3, line 60),
wherein the first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view (Figs. 1A-B).
Regarding to claim 2, Lin teaches the first dummy pattern comprises a plurality of dummy patterns disposed on the same plane, and the dummy patterns comprise a plurality of line patterns disposed adjacent to the four sides of the quadrangle shape of the first semiconductor substrate from the plan view and spaced apart from each other (Fig. 1A, the first dummy pattern comprises a plurality of dummy patterns 30B disposed on the same plane, and the dummy patterns comprise a plurality of line patterns disposed adjacent to the four sides of the quadrangle shape of the first semiconductor substrate from the plan view and spaced apart from each other).
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Claims 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chuang et al. (U.S. Patent No. 11,018,113).
Regarding to claim 21, Chuang teaches a semiconductor device comprising:
a first semiconductor chip (Fig. 1M, element 320), the first semiconductor chip comprising:
a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface (Fig. 1M, column 9, lines 25-27, the first surface is the bottom surface in the figure, the second surface is the top surface), the first semiconductor substrate having a quadrangle shape from a plan view (Fig. 2);
a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate and connected to the first active layer (Fig. 1M, the through vias through the substrate, please see the attached reproduced figure 1M with annotations);
a plurality of second chip connection pads on the second surface of the first semiconductor substrate and respectively connected to the plurality of first through electrodes (Fig. 1M, please see the attached reproduced figure 1M with annotations);
a plurality of protruding line patterns positioned outside the plurality of second chip connection pads on the second surface of the first semiconductor substrate from the plan view, each line pattern of the plurality of protruding line patterns extending horizontally along the second surface of the first semiconductor substrate (Fig. 1M, elements 280, please see Fig. 2 for plan view); and
a plurality of first chip connection pads on the first surface of the first semiconductor substrate and respectively connected to the plurality of first through electrodes (Fig. 1M, please see the attached reproduced figure 1M with annotations),
wherein the plurality of protruding line patterns are disposed adjacent to respective sides of the quadrangle shape of the first semiconductor substrate from the plan view (Fig. 2, layer 130 in the figure is on top and has same shape with element 280).
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Regarding to claim 22, Chuang teaches each protruding line pattern of the plurality of protruding line patterns has a bar shape extending adjacent to a respective side of the quadrangle shape along only a portion of the respective side (Fig. 1M, Fig. 2).
Regarding to claim 23, Chuang teaches the plurality of protruding line patterns are formed of the same material as the first semiconductor substrate or of a different, insulating material (Fig. 1M, protruding line patterns 280 are molding material, which is different from the semiconductor material).
Claims 21-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chuang et al. (U.S. Patent No. 11,018,113, different from the rejection above with same reference, in this rejection, other elements of the reference are cited for satisfying the requirements of dependent claims).
Regarding to claim 21, Chuang teaches a semiconductor device comprising:
a first semiconductor chip (Fig. 1L, please see the attached reproduced figure 1L with annotations), the first semiconductor chip comprising:
a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface (Fig. 1L, the fist semiconductor substrate including left and right elements 270, the first surface is the bottom surface in the figure, the second surface is the top surface), the first semiconductor substrate having a quadrangle shape from a plan view (Fig. 2);
a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate and connected to the first active layer (Fig. 1L, the through vias through the substrate, please see the attached reproduced figure 1L with annotations);
a plurality of second chip connection pads on the second surface of the first semiconductor substrate and respectively connected to the plurality of first through electrodes (Fig. 1L, please see the attached reproduced figure 1L with annotations);
a plurality of protruding line patterns positioned outside the plurality of second chip connection pads on the second surface of the first semiconductor substrate from the plan view, each line pattern of the plurality of protruding line patterns extending horizontally along the second surface of the first semiconductor substrate (Fig. 1L, elements 240, please see Fig. 2 for plan view); and
a plurality of first chip connection pads on the first surface of the first semiconductor substrate and respectively connected to the plurality of first through electrodes (Fig. 1L, please see the attached reproduced figure 1L with annotations),
wherein the plurality of protruding line patterns are disposed adjacent to respective sides of the quadrangle shape of the first semiconductor substrate from the plan view (Fig. 2, layer 130 in the figure is on top and has same shape with element 240).
Regarding to claim 22, Chuang teaches each protruding line pattern of the plurality of protruding line patterns has a bar shape extending adjacent to a respective side of the quadrangle shape along only a portion of the respective side (Fig. 1L, Fig. 2).
Regarding to claim 23, Chuang teaches the plurality of protruding line patterns are formed of the same material as the first semiconductor substrate or of a different, insulating material (Fig. 1L, protruding line patterns 240 are molding material, which is different from the semiconductor material).
Regarding to claim 24, Chuang teaches
a second semiconductor chip disposed on the second surface of the first semiconductor chip (Fig. 1L, please see the attached reproduced figure 1L with annotations); and
an adhesive layer formed between the second semiconductor chip and the second surface of the first semiconductor chip (Fig. 1L, please see the attached reproduced figure 1L with annotations);
wherein the adhesive layer surrounds and contacts the plurality of protruding line patterns (Fig. 1L).
Regarding to claim 25, Chuang teaches the adhesive layer extends horizontally beyond side surfaces of the first semiconductor chip and the second semiconductor chip (Fig. 1L).
Regarding to claim 26, Chuang teaches an encapsulation layer formed to surround the side surfaces of the first and second semiconductor chips and side surfaces of the adhesive layer (Fig. 1L, element 350).
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Allowable Subject Matter
Claims 8-14, 17-20, and 27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 8, the prior art fails to anticipate or render obvious the claimed limitations including “a second semiconductor chip mounted on the first semiconductor chip; and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip… wherein the first adhesive layer surrounds the second chip connection pad, the third chip connection pad, the first connection terminal, and the first dummy pattern” in combination with the limitations recited in claim 1 and the rest of limitations recited in claim 8.
Regarding to claim 27, the prior art fails to anticipate or render obvious the claimed limitations including “plurality of protruding line patterns are dam structures that control the flow of an adhesive material that forms the adhesive layer” in combination with the limitations recited in claim 21 and claim 24.
Pertinent Art
For the benefits of the Applicant, US-9275968-B2, US-9299736-B2, US-9224697-B1, US-7547975-B2, US-8299633-B2, US-10818640-B1, US-10665582-B2, US-10043769-B2, US-11855003-B2, US-11239203-B2, US-11508707-B2, US-11145639-B2, and US-11901333-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. In particular, these references disclose most features of the claims but fail to disclose the combination of limitations including “a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a line pattern extending horizontally along the second surface of the first semiconductor substrate; wherein the first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view, a second semiconductor chip mounted on the first semiconductor chip; and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897