Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Semiconductor transistor device including a plurality of dummy bodies within metal gate structure and method of fabricating the same”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8-14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hikida (US 20120168869).
Regarding claim 1. Fig 1 of Hikida discloses A semiconductor device, comprising:
a substrate 1;
a metal gate structure 9B/9A/9C ([0067]: ‘metal material’), disposed on the substrate;
at least one dummy body 11 (the 11 between 9B and 9A, and between 9A and 9C, which is silicon oxide film. Thus, being dummy body within metal gate) disposed within the metal gate structure;
two source/drain regions 12/7 [0056], respectively disposed in the substrate, at two sides of the metal gate structure (left and right sides); and
a dielectric layer 14 [0100], disposed on the substrate, around the metal gate structure.
Regarding claim 2. Hikida discloses The semiconductor device according to claim 1, wherein the at least one dummy body comprises a multilayer structure (Fig 1).
Regarding claim 3. Hikida discloses The semiconductor device according to claim 1, further comprising a plurality of the dummy bodies separately arranged in the metal gate structure (Fig 1).
Regarding claim 8. Hikida discloses The semiconductor device according to claim 3, wherein the dummy bodies are arranged in a symmetric pattern (Fig 1).
Regarding claim 9. Hikida discloses The semiconductor device according to claim 8, wherein the dummy bodies are arranged in an array pattern (Fig 1: in horizontal direction).
Regarding claim 10. Hikida discloses The semiconductor device according to claim 8, wherein the dummy bodies are extended along a same direction (Fig 1).
Regarding claim 11. Hikida discloses The semiconductor device according to claim 8, wherein the dummy bodies are arranged by a same pitch (Fig 11: by 11).
Regarding claim 12. Hikida discloses The semiconductor device according to claim 3, wherein the metal gate structure further comprises a plurality of gate units 9B/9A/9C, each of the gate units and each of the dummy bodies are alternately arranged in the metal gate structure (Fig 1).
Regarding claim 13. Hikida discloses The semiconductor device according to claim 12, wherein at least two of the gate units are in a same length (Fig 1: 9B vs 9C).
Regarding claim 14. Hikida discloses The semiconductor device according to claim 12, wherein at least two of the gate units are in different lengths (Fig 1, [0038]: 9A vs 9B).
Regarding claim 16. Hikida discloses A method of fabricating a semiconductor device, comprising:
providing a substrate 1 (Fig 2(a));
forming a metal gate structure 9B/9A/9C (Fig 3(e), [0067]: ‘metal material’; [0090]: each gate parts formed by patterning) on the substrate;
forming at least one dummy body 11 (the 11 between 9B and 9A, between 9A and 9C, which is silicon oxide film. Thus, being dummy body within metal gate) within the metal gate structure (Fig 3(f));
forming two source/drain regions 12/7 in the substrate, respectively at two sides of the metal gate structure (Fig 4(g)); and
forming a dielectric layer 14 [0100] on the substrate, around the metal gate structure (Fig 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hikida (US 20120168869) in view of Chuang (US 20120001259).
Regarding claim 15. Hikida discloses The semiconductor device according to claim 12 except each of the gate units comprises an U-shaped high-k dielectric layer, an U-shaped work function metal layer, an U-shaped barrier layer and a metal layer stacked from bottom to top.
However, Fig 10 (device 12) of Chuang discloses an U-shaped high-k dielectric layer 44 [0019], an U-shaped work function metal layer 56, an U-shaped barrier layer 52 and a metal layer 60 stacked from bottom to top [0021]-[0023].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Hikida’s device to have the Chuang’s gate structure for the purpose of providing enhanced electrostatic control, shrinking device size (EOT), reducing power leakage, and improving drive current with enhanced gate coverage and surface area.
Allowable Subject Matter
Claims 4-7 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the dummy bodies are arranged in an asymmetric pattern”.
Regarding claim 17. Regarding claim 1. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “forming at least one poly slot within the polysilicon gate structure; forming the at least one dummy body filled in the at least one poly slot; and after removing the polysilicon gate structure, forming the metal gate structure”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812