DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “varying” in claim 20 is a relative term which renders the claim indefinite. The term “varying” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
As understood by the Examiner, all manufacturing processes have some amount of variation, either by intended process targets or natural process variability. Since no particular degree of thickness change and/or thickness profile is recited in the claim, the Examiner has interpreted this term to broadly include natural process variation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9-13 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kyler et al. (Patent No. US 6,334,929 B1).
Regarding claim 1, Kyler teaches a method for processing a semiconductor wafer, the method comprising:
providing a high resistivity wafer (col. 1 lines 66-67, col. 2 line 37 & fig. 2: 22) having a back side (col. 2 line 45: 27) and a front side (col. 2 line 37: 23);
doping one side of the high resistivity wafer (col. 2 lines 39-43) to form a doped layer having an increased conductivity on the one side of the high resistivity wafer (col. 2 lines 36-39 & fig. 2: doped layer comprising conductive plane 28 formed on back side 27); and
performing a plasma-based process on the other side of the high resistivity wafer (col. 2 lines 39-43), the doped layer affecting at least one of an etch rate and a deposition rate during the plasma- based process so as to facilitate improved uniformity in thickness of a layer resulting from the plasma-based process (col. 2 lines 6-7, col. 3 lines 35-37 & fig. 4: 28 improves surface uniformity of the substrate undergoing a front side plasma process, such as an etch).
Regarding claim 2, Kyler teaches the method of claim 1 wherein the doped layer is formed on the back side of the high resistivity wafer (fig. 2: 28 formed on back side 27) and the plasma-based process is performed on the front side of the high resistivity wafer (col. 2 lines 36-57, col. 3 lines 44-46 & fig. 2: plasma process performed on layers 24 and 26 on front surface 23).
Regarding claim 3, Kyler teaches the method of claim 2 wherein the doped layer covers substantially the entire area of the back side of the high resistivity wafer (fig. 2: 28 covers substantially the entire area of 27).
Regarding claim 4, Kyler teaches the method of claim 2 wherein the doped layer is formed using a diffusion process (col. 2 lines 35-55: 28 formed by implant/anneal which implicitly includes some amount of dopant diffusion).
Regarding claim 5, Kyler teaches the method of claim 2 wherein the doped layer is formed using an ion implantation process (col. 2 lines 35-55).
Regarding claim 9, Kyler teaches the method of claim 2 wherein the plasma-based process includes an etching process (col. 3 lines 43-47 & 60-62).
Regarding claim 10, Kyler teaches the method of claim 2 wherein the layer resulting from the plasma-based process includes a nitride layer (col. 3 lines 43-47 & 60-62).
Regarding claim 11, Kyler teaches the method of claim 2 wherein the improved uniformity includes a reduction in relative standard deviation of measured thickness values by a factor of at least two when compared to similar thickness values corresponding to a high resistivity wafer without a doped layer on its back side (col. 3 lines 51-63 & fig. 4: standard deviation of curve 32 lower than standard deviation of curve 30 by at least a factor of two).
Regarding claim 12, Kyler teaches the method of claim 1 wherein providing the high resistivity wafer includes providing one of a silicon or a gallium arsenide wafer (col. 1 lines 4-7, claim 6).
Regarding claim 13, Kyler teaches the method of claim 1 further comprising removing the doped layer after performing the plasma-based process (col. 3 lines 14-17: conductive plane removed by conventional techniques).
Regarding claim 20, Kyler teaches a method to process a high resistivity semiconductor wafer, the method comprising:
providing the high resistivity semiconductor wafer (col. 1 lines 66-67, col. 2 line 37 & fig. 2: 22);
doping a back side of the high resistivity semiconductor wafer (col. 2 lines 39-43) to form a doped layer on the back side of the high resistivity semiconductor wafer (col. 2 lines 36-39 & fig. 2: doped layer comprising conductive plane 28 formed on back side 27); and
performing a plasma-based process according to a front-side design on a front side of the high resistivity semiconductor wafer (col. 2 lines 39-43), the doped layer including varying thickness profiles (‘varying’ is a relative term not defined/limited by the claim: all known implant processes have inherent variation in localized depth, and therefore meet the broadest reasonable interpretation of ‘varying thickness profiles’) to accommodate the front-side design (Plasma process performed on front side of 22), the varying thickness profiles of the doped layer affecting at least one of an etch rate and a deposition rate during the plasma-based process (col. 2 lines 6-7, col. 3 lines 35-37 & fig. 4: 28 improves surface uniformity of the substrate undergoing a front side plasma process, such as an etch).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kyler as applied to claim 2 above, and further in view of Liu et al. (Patent No. US 9,508,597 B1).
Regarding claim 4, Kyler teaches the method of claim 2 comprising a doped layer (28).
Kyler does not teach wherein the doped layer is formed using a diffusion process.
Liu teaches a method including forming a doped layer (col. 6 line 67: 50) using a diffusion process (col. 7 lines 6-7: 50 formed by diffusion impurities from a non-illustrated epitaxial doping layer).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Kyle with a diffusion process, as a means to avoid defects such as crystal damage resulting from doping processes such as ion implantation.
Furthermore, an express suggestion to substitute one equivalent component or process for another is not necessary to render such substitution obvious. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982). In the instant case, epitaxial deposition is a suitable alternative process to the ion implantation of Kyler for forming doped layers.
Regarding claim 6, Kyler teaches the method of claim 2, comprising a doped layer (28).
Kyler does not teach wherein the doped layer is formed using an epitaxial deposition process.
Liu teaches a method including forming a doped layer (col. 6 line 67: 50) using an epitaxial deposition process (col. 7 lines 6-7: 50 formed using a non-illustrated epitaxial doping layer).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Kyle with an epitaxial deposition process, as a means to avoid defects such as crystal damage resulting from doping processes such as ion implantation.
Furthermore, an express suggestion to substitute one equivalent component or process for another is not necessary to render such substitution obvious. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982). In the instant case, epitaxial deposition is a suitable alternative process to the ion implantation of Kyler for forming doped layers.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kyler as applied to claim 1 above, and further in view of Cheng ("Improving Front Side Process Uniformity by Back-Side Metallization," CS MANTECH Conference, April 23rd - 26th, 2012, Boston, Massachusetts, USA).
Regarding claims 7-8, Kyler teaches the method of claim 2, comprising a plasma-based process (col. 3 lines 43-47 & 60-62).
Kyler does not teach wherein the plasma-based process includes a deposition process, wherein the deposition process includes a plasma-enhanced chemical vapor deposition (PECVD) process.
Cheng teaches a method including performing a plasma-based deposition process (p. 4 col. 1 lines 3-6), wherein the deposition process includes a plasma-enhanced chemical vapor deposition (PECVD) process (p. 1 col. 2 lines 21-26).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the plasma process of Kyler to include a PECVD deposition process, as a means to form a uniform nitride layer on a front side of highly resistive wafers, improving yield (Cheng, p. 4 col. 1 lines 4-5).
Claims 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kyler in view of Cheng.
Regarding claim 14, Kyler teaches a method for processing a high resistivity semiconductor wafer, the method comprising:
providing the high resistivity semiconductor wafer (col. 1 lines 4-7, claim 6); and
doping on one side of the high resistivity semiconductor wafer to form a doped layer on the one side of the high resistivity semiconductor wafer (col. 2 lines 38-39 & fig. 2: conductive plane 28 (internal to GaAs substrate 22) is formed beneath a back surface 27 of GaAs substrate 22) to reduce variation during a plasma-based process on the other side of the high resistivity semiconductor wafer (col. 3 lines 40-43: gross nonuniformity across the surface of the substrate as well as localized areas of nonuniformity can be improved), the reduced variation facilitating improved uniformity in at least one of an etch rate and a deposition rate during the plasma-based process (col. 2 lines 6-7, col. 3 lines 35-37 & fig. 4: 28 improves surface uniformity of the substrate undergoing a front side plasma process, such as an etch).
Kyler is silent to the doped layer reducing variation in radio- frequency (RF) coupling during a plasma-based process.
Cheng teaches that reduced resistivity and/or increased conductivity of GaAs wafers improves RF coupling during a plasma process (p. 1 col. 1 lines 20-22: high resistivity of the substrate inhibits efficient coupling of RF power and exhibits non-uniformity, and p. 2 table 1: wafers with lower backside resistivity have improved uniformity).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Kyle to include reduced variation in radio- frequency (RF) coupling during a plasma-based process, as a means to minimize standard deviation of a thickness during a front-side plasma process (Cheng, p. 2 col. 2 line 20 – p. 3 col. 1 line 2).
Regarding claim 15, Kyler in view of Cheng teaches the method of claim 14 further comprising performing the plasma-based process on the other side of the high resistivity semiconductor wafer (Kyler, col. 2 lines 36-57, col. 3 lines 44-46 & fig. 2: plasma process performed on layers 24 and 26 on front surface 23).
Regarding claim 16, Kyler in view of Cheng teaches the method of claim 14 further comprising removing the doped layer after the plasma-based process (Kyler, col. 3 lines 14-17: conductive plane removed by conventional techniques).
Regarding claim 17, Kyler in view of Cheng teaches the method of claim 14 wherein the variation in RF coupling includes a contribution from one or more features defined by or associated with a wafer handling device (Cheng, p. 3 col. 2 lines 12-16: cavity in the wafer chuck such as lift-pin holes or wafer-handler recess in the platen alter the capacitive and RF power coupling effectiveness and affect the etch and deposition rates).
Regarding claim 18, Kyler in view of Cheng teaches the method of claim 17 wherein the wafer handling device includes a wafer platen (Cheng: p. 1 col. 2 line 21 & fig. 1).
Regarding claim 19, Kyler in view of Cheng teaches the method of claim 17 wherein the wafer handling device includes a wafer chuck (Cheng: p. 2 col. 2 line 4 & fig. 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818
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