DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
In view of applicant’s amendments and arguments filed on March 20, 2026, the rejections of claims 1-5, 7-9, 12 and 14-20 under 35 U.S.C. 112(b) or 102 as stated in the Office Action mailed on December 23, 2025 have been withdrawn.
Applicant’s amendments and arguments have been rendered moot in view of the new or modified ground of rejection given below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 12 and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US Pub. 2018/0286956; hereinafter “Xie”).
Regarding Claim 1, Xie discloses a semiconductor device comprising: an active region 102X (page 4, paragraph 23); a gate region 104 (page 4, paragraph 23); a first gate electrode 106 (gates without a gate cap material 127; see fig. 2J); a second gate electrode 106 (gates with the gate cap material; see fig. 2J) having a height that is less than a height of the first gate electrode 106 (see fig. 2J); and a gate contact (CB) 135 (page 6, paragraph 37) formed on the first gate electrode 106 (see fig. 2L), the gate contact (CB) 135 overlapping with the active region 102X and extending beyond the gate region 104 in plan view (see figs. 2J and 2L).
Regarding Claim 2, Xie discloses further comprising a source/drain epitaxial layer 114 (page 4, paragraph 23).
Regarding Claim 3, Xie discloses further comprising a source/drain contact 121 (page 4, paragraph 25) formed on the source/drain epitaxial layer 114 (see fig. 2L).
Regarding Claim 4, Xie discloses wherein a top surface (121R, 121Y) (page 5, paragraphs 31 and 32; see fig. 2J) of the source/drain contact 121 is at or below a bottom surface of the gate contact 135 (see fig. 2L).
Regarding Claim 12, Xie discloses further comprising: a source/drain epitaxial layer 114 (page 4, paragraph 23); a source/drain contact 121 (page 4, paragraph 25) formed on the source/drain epitaxial layer 114 (see fig. 2L); and a gate spacer 108 (page 4, paragraph 23) formed on sides of the source/drain contact 121 (see fig. 2L).
Regarding Claim 15, Xie discloses a method of manufacturing a semiconductor device, the method comprising: forming an active region 102X (page 4, paragraph 23); forming a gate region 104 (page 4, paragraph 23); forming a first gate electrode 106 (gates without a gate cap material 127; see fig. 2J); forming a second gate electrode 106 (gates with the gate cap material; see fig. 2J) having a height that is less than a height of the first gate electrode 106 (see fig. 2J); and forming a gate contact (CB) 135 (page 6, paragraph 37) formed on the first gate electrode 106 (see fig. 2L), the gate contact (CB) 135 overlapping with the active region 102X and extending beyond the gate region 104 in plan view (see figs. 2J and 2L).
Regarding Claim 16, Xie discloses further comprising forming a source/drain epitaxial layer 114 (page 4, paragraph 23).
Regarding Claim 17, Xie discloses further comprising forming a source/drain contact 121 (page 4, paragraph 25) on the source/drain epitaxial layer 114 (see fig. 2L).
Regarding Claim 18, Xie discloses wherein a top surface (121R, 121Y) (page 5, paragraphs 31 and 32; see fig. 2J) of the source/drain contact 121 is at or below a bottom surface of the gate contact 135 (see fig. 2L).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7-9, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Kim et al. (US Pub. 2021/0233847; hereinafter “Kim”).
Regarding Claims 7 and 20, Xie fails to disclose explicitly wherein the first gate electrode includes a first raised portion and a second raised portion, the second raised portion having a greater height than the first raised portion.
However, Kim discloses wherein a first gate electrode 110 including a first raised portion 110_2 and a second raised portion 110_1, wherein the second raised portion 110_1 has a greater height than the first raised portion 110_2 (page 3, paragraph 40; see fig. 10).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide two portions of a gate electrode having different heights, as taught by Kim, in order to reduce parasitic capacitance and increase electrical stability between contacts (Kim; page 1, paragraph 3).
Regarding Claim 8, Xie discloses wherein a recess (a recess is formed in a layer of insulating material 133, wherein the gate contact (CB) 135 is formed in the recess; page 6, paragraph 37; see fig. 2L) is formed in an area above the first gate electrode 106 (see fig. 2L), and Kim discloses the first gate electrode includes the first raised portion 110_2 and adjacent to the second raised portion 110_1 (see rejection of claim 7 above).
Regarding Claim 9, Xie discloses further comprising an interlayer dielectric (ILD) layer 133 (page 6, paragraph 37) formed over the second gate electrode 106 (see fig. 2L).
Regarding Claim 14, Xie fails to disclose explicitly wherein the first gate electrode and the second gate electrode are formed as a nanosheet stack structure including alternating layers of a semiconductor layer and a high-k metal gate layer.
However, Kim discloses wherein a first gate electrode 110 and a second gate electrode 120 are formed as a nanosheet stack structure (see fig. 14) including alternating layers of a semiconductor layer NW1, NW2 (page 7, paragraphs 112 and 113) and a high-k metal gate layer (111/110, 121/120) (a gate insulating film 111, 112 is formed of a high-k dielectric material; page 3, paragraph 47; and the gate electrodes 110, 120 are formed of a metal; page 4, paragraph 52; thereby constituting a high-k metal gate layer).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a nanosheet stack structure for gate structures, as taught by Kim, in order to improve gate control over the channel region, thereby reducing short-channel effects and improving transistor performance and scalability in advanced semiconductor devices.
Allowable Subject Matter
Claims 5, 6, 10, 11, 13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 recites a source/drain contact residual portion formed over the second gate electrode.
Claim 6 recites a center of the gate contact is offset from a center of the first gate electrode.
Claim 10 recites the ILD layer is also formed in the recess.
Claim 13 recites a source/drain contact residual portion formed over the second gate electrode, wherein the source/ drain contact residual portion is electrically isolated from the source/drain contact by the gate spacer.
Claim 19 recites forming a source/drain contact residual portion formed over the second gate electrode.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claim 11 depends from claim 10, so it is objected for the same reason.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 May 8, 2026
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