Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species A (Figure 9, claims 1-6 and 8-20) in the reply filed on 03/16/2026 is acknowledged.
Claim Objections
Claim 1 is objected to because of the following informalities: “on provided” should be changed to “provided on”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6, 8, 11-16 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US Pub. No. 2020/0105889 A1) in view of Wilting (US Patent No. 4,373,251).
As to claim 1, Liaw discloses an integrated circuit semiconductor device (fig 28, 200D) comprising:
a nanosheet (fig 28, 210A) provided on a substrate (201), the nanosheet extending in a first horizontal direction (horizontal cross-sectional direction shown in fig 28);
a gate electrode (255) comprising a first gate electrode portion provided on an upper side of the nanosheet (portion of 255 on upper side of 210A) and a second gate electrode portion provided on a lower side of the nanosheet (portion of 255 on lower side of 210A), the gate electrode extending in a second horizontal direction that is perpendicular to the first horizontal direction (fig 28 direction perpendicular to the cross-section);
a gate insulating layer (252) provided between the gate electrode (255) and the nanosheet (210A);
a first source/drain region (s/d comprising 240 and 230 on the right side of nanosheet 210A) provided on a first side of the nanosheet corresponding to the gate electrode (255); and
a second source/drain region (s/d comprising 240 and 230 on the left side of nanosheet 210A) provided on a second side of the nanosheet corresponding to the gate electrode (255),
wherein the first source/drain region (240/230) comprises:
first silicide layers comprising a first upper silicide layer (upper layer portion of 240 on top surface of 210A) provided on the nanosheet (210A), and a first lower silicide layer (lower layer portion of 240 on bottom surface of 210A) on provided the nanosheet (210A),
a first upper metal layer (portion of 230) provided on the first upper silicide layer (240) and a first lower metal layer (portion of 230) provided on the first lower silicide layer (240), and
a first nanosheet region (210A) provided between the first upper silicide layer (upper portion of 240) and the first lower silicide layer (lower portion of 240),
wherein the second source/drain region (s/d 230/240 on left side) comprises:
second silicide layers comprising a second upper silicide layer (upper layer portion of 240 on top surface of 210A) provided on the nanosheet (210A), and a second lower silicide layer (lower layer portion of 240 on bottom surface of 210A) provided on the nanosheet (210A),
a second upper metal layer (230) provided on the second upper silicide layer (upper portion of 240) and a second lower metal layer (230) provided on the second lower silicide layer (lower portion of 240), and
a second nanosheet region (210A) provided between the second upper silicide layer (upper 240) and the second lower silicide layer (lower 240).
Liaw does not explicitly disclose that the silicidation process forms the silicide 240 extending inward of the upper and lower surfaces of the nanosheet.
Nonetheless, Wilting discloses that a silicidation process between a semiconductor layer and a metal layer converts at least a part of the thickness of the semiconductor layer into a silicide layer (col. 2, lines 50-60).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the silicide layer such that it extends inward from the surface of the semiconductor layer of Liaw as taught by Wilting since this will ensure that the thermal treatment enables the chemical reaction that creates the silicide layer between the metal and the semiconductor nanosheet.
As to claim 2, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 1 (paragraphs above).
Liaw further discloses wherein the nanosheet extends from the gate electrode to the first source/drain region in the first horizontal direction and extends from the gate electrode to the second source/drain region in a first reverse horizontal direction (fig 28, NS 210A from s/d on left to s/d on right.
As to claim 3, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 1 (paragraphs above).
Liaw further discloses wherein the nanosheet comprises a single layer which continuously extends in the first horizontal direction (fig 28, 210A).
As to claim 4, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 1 (paragraphs above).
Liaw further discloses wherein the nanosheet is spaced apart from a surface of the substrate (fig 28, substrate 201 and NS 210A), and a thickness of the nanosheet in a first vertical direction is greater than a thickness of the nanosheet in the second horizontal direction, the first vertical direction being perpendicular to the first and second horizontal directions (NS210A as combined with Wilting above).
As to claim 5, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 1 (paragraphs above).
Liaw further discloses wherein the nanosheet has a first thickness in a first region between the first gate electrode portion and the second gate electrode portion and a second thickness in a second region between the first upper silicide layer and the first lower silicide layer or between the second upper silicide layer and the second lower silicide layer, the first thickness being different from the second thickness (NS210A as combined with Wilting above).
As to claim 6, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 1 (paragraphs above).
Liaw further discloses wherein each of the first silicide layers and the second silicide layers comprises metal silicide layers or polycide layers ([0044]).
As to claim 8, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 1 (paragraphs above).
Liaw further discloses a first spacer (fig 28, spacer 220 on right) provided between the gate electrode (255) and the first source/drain region (230/240); and a second spacer (spacer 220 on left) provided between the gate electrode (255) and the second source/drain region (230/240).
As to claim 11, Liaw discloses an integrated circuit semiconductor device (fig 28) comprising:
a plurality of nanosheets (fig 28, 210A) provided on a substrate (201), the plurality of nanosheets extending in a first horizontal direction and being spaced apart from a surface of the substrate and spaced apart from each other in a first vertical direction that is perpendicular to the first horizontal direction (see vertical and horizontal direction shown in fig 28);
a gate electrode (255) comprising a plurality of gate electrode portions provided on the plurality of nanosheets (portions of 255 on 210A), the gate electrode extending in a second horizontal direction that is perpendicular to the first horizontal direction (fig 28, horizontal direction to the cross-section in fig 28);
a plurality of gate insulating layers (252) provided between the plurality of gate electrode portions (255) and the plurality of nanosheets (210A);
a first source/drain region (230/240) provided on a first side (right side) of the plurality of nanosheets (210A) corresponding to the gate electrode (255); and
a second source/drain region (230/240) provided on a second side (left side) of the plurality of nanosheets (210A) corresponding to the gate electrode (255),
wherein the first source/drain region (240/230 on the right) comprises:
first silicide layers (240) comprising a first upper silicide layer provided on a first nanosheet (upper 240 on 210A), among the plurality of nanosheets, and a first lower silicide layer on provided the first nanosheet (lower 240 on 210A),
a first upper metal layer (upper 230) provided on the first upper silicide layer (upper 240),
a first lower metal layer (lower 230) provided on the first lower silicide layer (lower 240), and
a first nanosheet region (210A) provided between the first upper silicide layer (upper 240) and the first lower silicide layer (lower 240), and
wherein the second source/drain region (230/240 on the left) comprises:
second silicide layers (240 on the left side) comprising a second upper silicide layer provided on the first nanosheet (upper 240 on 210A), and
a second lower silicide layer provided on the first nanosheet (lower 240 on 210A),
a second upper metal layer (upper 230) provided on the second upper silicide layer (upper 240),
a second lower metal layer (lower 230) provided on the second lower silicide layer (lower 240), and
a second nanosheet region provided between the second upper silicide layer and the second lower silicide layer (210 between upper 240 and lower 240).
Liaw does not explicitly disclose that the silicidation process forms the silicide 240 extending inward of the upper and lower surfaces of the nanosheet.
Nonetheless, Wilting discloses that a silicidation process between a semiconductor layer and a metal layer converts at least a part of the thickness of the semiconductor layer into a silicide layer (col. 2, lines 50-60).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the silicide layer such that it extends inward from the surface of the semiconductor layer of Liaw as taught by Wilting since this will ensure that the thermal treatment enables the chemical reaction that creates the silicide layer between the metal and the semiconductor nanosheet.
As to claim 12, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 11 (paragraphs above).
Liaw further discloses wherein each of the plurality of nanosheets comprises a single layer continuously extending from the gate electrode to the first source/drain region in the first horizontal direction and continuously extending from the gate electrode to the second source/drain region in a first reverse horizontal direction (fig 28, NS 210A).
As to claim 13, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 11 (paragraphs above).
Liaw further discloses wherein each of the first source/drain region and the second source/drain region comprise non-epitaxial growth layers ([0022]).
As to claim 14, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 11 (paragraphs above).
Liaw further discloses wherein the first upper metal layer is provided above the first nanosheet, which is an uppermost nanosheet among the plurality of nanosheets (fig 28, upper metal layer 230 is above uppermost 210A), and
wherein the first lower metal layer provided on the first nanosheet and a second nanosheet, among the plurality of nanosheets (fig 28, lower 230 provided on 210A).
As to claim 15, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 11 (paragraphs above).
Liaw further discloses channel regions in the plurality of nanosheets between the plurality of gate electrode portions (fig 28, channel regions of 210A corresponding to gate 255), and
non-channel regions in the plurality of nanosheets between the first upper silicide layer and the first lower silicide layer or between the second upper silicide layer and the second lower silicide layer, the-channel regions being in contact with the first and second source/drain regions (fig 28, non-channels of 210, s/d 240/230).
As to claim 16, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 11 (paragraphs above).
Liaw further discloses a first spacer provided between the gate electrode and the first source/drain region (220 between 255 and s/d on right); and
a second spacer provided between the gate electrode and the second source/drain region (220 between 255 and s/d on left).
As to claim 18, Liaw discloses an integrated circuit semiconductor device (fig 28) comprising:
a lower nanosheet (fig 28, bottom NS 210A) provided on a substrate (201), the lower nanosheet extending in a first horizontal direction (horizontal direction of cross-section shown in fig 28);
an upper nanosheet (upper NS 210A) provided on the substrate (201), the upper nanosheet extending in the first horizontal direction and being apart from a surface of the substrate in a first vertical direction that is perpendicular to the first horizontal direction (upper and lower 210A);
an isolation-insulating layer (220 adjacent to 235) configured to insulate the lower nanosheet and the upper nanosheet from each other (upper and lower 210A);
a gate electrode (255) comprising a plurality of gate electrode portions provided on the upper and lower nanosheets (210A), the gate electrode extending in a second horizontal direction perpendicular to the first horizontal direction (horizontal direction perpendicular to cross-sectional view shown in fig 28);
a first source/drain region (230/240 on the right) provided on a first side of the lower and upper nanosheets (210A) corresponding to the gate electrode (255); and
a second source/drain region (230/240 on the left) formed on a second side of the lower and upper nanosheets (210A) with corresponding to the gate electrode (255),
wherein the first source/drain region (230/240 on right) comprises:
first silicide layers (layer of 240 on 210A) comprising a first upper silicide layer provided on the lower nanosheet and upper nanosheet (240 on 210A), and a first lower silicide layer on provided the lower nanosheet (240 on 210A),
a first upper metal layer (upper 230) provided on the first upper silicide layer (upper 240), a first lower metal layer provided on the first lower silicide layer (lower 230 on lower 240), and
a first nanosheet region provided between the first upper silicide layer and the first lower silicide layer (NS region 210A between upper and lower 240), and
wherein the second source/drain region (230/240 on the left) comprises:
second silicide layers comprising a second upper silicide layer provided on the lower nanosheet and upper nanosheet (upper 240 on 210A), and a second lower silicide layer provided on the lower nanosheet and upper nanosheet (lower 240 on 210A),
a second upper metal layer (upper 230) provided on the second upper silicide layer (upper 240),
a second lower metal layer (lower 230) provided on the second lower silicide layer (lower 240), and
a second nanosheet region provided between the second upper silicide layer and the second lower silicide layer (NS region 210A between upper and lower 240).
Liaw does not explicitly disclose that the silicidation process forms the silicide 240 extending inward of the upper and lower surfaces of the nanosheet.
Nonetheless, Wilting discloses that a silicidation process between a semiconductor layer and a metal layer converts at least a part of the thickness of the semiconductor layer into a silicide layer (col. 2, lines 50-60).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the silicide layer such that it extends inward from the surface of the semiconductor layer of Liaw as taught by Wilting since this will ensure that the thermal treatment enables the chemical reaction that creates the silicide layer between the metal and the semiconductor nanosheet.
As to claim 19, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 11 (paragraphs above).
Liaw further discloses wherein each of the upper nanosheet and the lower nanosheet comprises a single layer which continuously extends from the gate electrode to the first source/drain region in the first horizontal direction and extends from the gate electrode to the second source/drain region in a first reverse horizontal direction (fig 28, upper and lower 210A).
Claim(s) 9-10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Wilting and further in view of Chen et al. (US Pub. No. 2024/0071941 A1), hereafter referred to as Chen.
As to claim 9, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 1 (paragraphs above).
Liaw in view of Wilting do not disclose a through-electrode provided in the substrate and electrically connected to the first and second source/drain regions, and
a backside power rail provided in a back surface of the substrate electrically connected to the through-electrode.
Nonetheless, Chen discloses a through-electrode provided in a substrate and electrically connected to first and second source/drain regions (fig 19, through electrode 1602 in substrate 602 connected to s/d 1102), and
a backside power rail (1902) provided in a back surface of the substrate electrically connected to the through-electrode (1602).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the circuitry of Chen in the transistor device of Liaw in view of Wilting since this will improve miniaturization of the device by improving packaging of the semiconductor device.
As to claim 10, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 1 (paragraphs above).
Liaw in view of Wilting do not disclose a first backside power rail provided in the substrate and electrically connected to the first and second source/drain regions,
a through-electrode provided in the substrate and electrically connected to the first backside power rail, and
a second backside power rail provided in a back surface of the substrate, and electrically connected to the through-electrode.
Nonetheless, Chen discloses a first backside power rail provided in the substrate and electrically connected to the first and second source/drain regions (fig 19, 1902),
a through-electrode provided in the substrate and electrically connected to the first backside power rail (1602 to 1902), and
a second backside power rail provided in a back surface of the substrate, and electrically connected to the through-electrode (adjacent 1902 connected to through-electrode that comprises left and right 1602).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the circuitry of Chen in the transistor device of Liaw in view of Wilting since this will improve miniaturization of the device by improving packaging of the semiconductor device.
As to claim 17, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 11 (paragraphs above).
Liaw in view of Wilting do not disclose a through-electrode formed in the substrate, the through-electrode being electrically connected to a backside power rail electrically connected to the first and second source/drain regions, and
contact electrodes connected to a wiring layer, the contact electrodes being formed in the first and second source/drain regions.
Nonetheless, Chen discloses a through-electrode formed in the substrate, the through-electrode being electrically connected to a backside power rail electrically connected to the first and second source/drain regions (fig 19, 1902, 1602), and
contact electrodes connected to a wiring layer, the contact electrodes being formed in the first and second source/drain regions (fig 13, 1302 and 1102).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the circuitry of Chen in the transistor device of Liaw in view of Wilting since this will improve miniaturization of the device by improving packaging of the semiconductor device.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Wilting and further in view of Hall et al. (US Pub. No. 2023/0290862 A1), hereafter referred to as Hall.
As to claim 20, Liaw in view of Wilting disclose the integrated circuit semiconductor device of claim 11 (paragraphs above).
Liaw further discloses a first spacer (220 adjacent to gate 255 on the right side) provided between the gate electrode (255) and the first source/drain region (230/240);
a second spacer (220 adjacent to gate 255 on the left side) provided between the gate electrode (255) and the second source/drain region (230/240).
Liaw in view of Wilting do not disclose wherein the isolation-insulating layer divides the plurality of gate electrode portions in the first vertical direction into first gate electrode portions corresponding to the lower nanosheet and second gate electrode portions corresponding to the upper nanosheet, and
wherein the isolation-insulating layer separates the first upper and lower metal layers and the second upper and lower metal layers.
Nonetheless, Hall discloses an isolation-insulating layer divides the plurality of gate electrode portions in the first vertical direction into first gate electrode portions corresponding to the lower nanosheet and second gate electrode portions corresponding to the upper nanosheet (fig 31, isolation-insulating layer 215/203 dividing gates 218 from 220 corresponding to 202 and 206), and
wherein the isolation-insulating layer separates the first upper and lower metal layers and the second upper and lower metal layers (fig 31, 215/203 separating 214/216 on left and right of the gate 220).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the isolation-insulating layer of Hall in the transistor device of Liaw in view of Wilting since this will electrically separate the upper nanosheet channels from the lower nanosheet channels thus allowing for independent operation of the upper and lower transistor regions.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhang et al. (US Pub. No. 2019/0181224 A1) teaches in fig 8 silicide layers 26 on upper surface and lower surface of nanosheet 14/22.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 4/21/2026
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