DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/21/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: BONDED SEMICONDUCTOR MEMORY DEVICE.
Allowable Subject Matter
Claims 11-12 and 15-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
A. Re claim 11, the prior art cannot anticipate, or render obvious the limitations of: wherein: the memory cell structure includes a cell gate structure, a cell capacitor, and a bit line between the cell gate structure and the cell capacitor, and the first upper bonding pad and the first lower bonding pad overlap the bit line, in combination with the claimed features of claim 9.
B. Re claim 12, the prior art cannot anticipate, or render obvious the limitations of: wherein the first upper bonding pad and the first lower bonding pad overlap the cell gate structure and the cell capacitor, in combination with the claimed features of claims 9 and 11.
C. Re claim 15, the prior art cannot anticipate, or render obvious the limitations of: wherein the lower bonding structure includes: a power capacitor between the lower substrate and the lower dielectric structure; and a second lower bonding pad electrically connected to the power capacitor, in combination with the claimed features of claim 9.
D. Re claim 16, the prior art cannot anticipate, or render obvious the limitations of: wherein the second upper bonding pad and the second lower bonding pad overlap the power capacitor, in combination with the claimed features of claims 9 and 15.
E. Re claim 17, the prior art cannot anticipate, or render obvious the limitations of: wherein the memory cell structure includes a cell capacitor, wherein the cell capacitor is at a level the same as a level of the power capacitor, in combination with the claimed features of claims 9 and 15.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the first upper contact" in line 4. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes, "the first upper contact" in line 4 will be interpreted to read as "the upper contact".
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-8; 9, 10, 13, 18, 19; and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by GAN et al (US 2021/0118988 A1, hereafter Gan).
Re claim 1, Gan discloses in FIG. 9 (with references to FIGS. 4-8) a semiconductor device (3D memory 900; [0119]), comprising:
a lower substrate (530; [0093]);
a lower dielectric structure (lower 690; [0104]-[0105]) on the lower substrate (530);
a memory cell structure (340 at 450B as in 540; [0093]) between the lower substrate (530) and the lower dielectric structure (lower 690);
a lower bonding pad (586 at 450B; [0105]) in the lower dielectric structure (lower 690);
an upper dielectric structure (upper 690; [0104]-[0105]) on the lower dielectric structure (lower 690);
an upper substrate (430; [0093]) on the upper dielectric structure (upper 690);
a transistor (450B; [0069]) between the upper substrate (430) and the upper dielectric structure (upper 690); and
an upper bonding pad (486 at 450B; [0105]) in the upper dielectric structure (upper 690), wherein:
a top surface (upper plane) of the lower bonding pad (586 at 450B) is in
contact with (connected at; [0107]) a bottom surface (lower plane) of the upper bonding
pad (486 at 450B), and
the lower bonding pad (586 at 450B) and the upper bonding pad (486 at 450B) overlap (partially cover) the memory cell structure (340 at 450B).
Re claim 9, Gan discloses in FIG. 9 (with references to FIGS. 4-8) a semiconductor device, comprising:
a lower bonding structure (500; [0093]) that includes a lower substrate (530; [0093]), a lower dielectric structure (lower 690; [0104]-[0105]) on the lower substrate (530), a memory cell structure (340 at 450B as in 540; [0093]) between the lower substrate (530) and the lower dielectric structure (lower 690), and a first lower bonding pad (586 of 450B; [0105]) in the lower dielectric structure (lower 690); and
an upper bonding structure (400; [0069]) that includes an upper dielectric structure (upper 690; [0104]-[0105]) on the lower dielectric structure (lower 690), an upper substrate (430; [0093]) on the upper dielectric structure (upper 690), a first transistor (450B; [0069]) between the upper substrate (430) and the upper dielectric structure (upper 690), and a first upper bonding pad (486 of 450B; [0105]) in the upper dielectric structure (upper 690), wherein the first lower bonding pad (586 of 450B) is in contact with the first upper bonding pad (486 of 450B),
wherein the first transistor (450B) overlaps (partially covers) the memory cell structure (340 at 450B), and wherein the first transistor (450B) is electrically connected ([0107]) to the memory cell structure (340 at 450B) through the first upper bonding pad (486 of 450B) and the first lower bonding pad (586 of 450B).
Re claim 20, Gan discloses in FIG. 9 (with references to FIGS. 4-8) a semiconductor device, comprising:
a lower substrate (530; [0093]);
a lower dielectric structure (lower 690; [0104]-[0105]) on the lower substrate (530);
a memory cell structure (340 at 450B as in 540; [0093]) between the lower substrate (530) and the lower dielectric structure (lower 690), wherein the memory cell structure (340 at 450B) includes a bit line (584 at 450B; [0099]);
an upper dielectric structure (upper 690; [0104]-[0105]) on the lower dielectric structure (lower 690);
an upper substrate (430; [0093]) on the upper dielectric structure (upper 690);
a transistor (450B; [0069]) between the upper substrate (430) and the upper dielectric structure (upper 690);
a connection dielectric structure (laminate 792/997; [0115] and [0122]) on the upper substrate (430);
a connection conductive structure (998; [0123]) in the connection dielectric structure (laminate 792/997);
a lower bonding pad (586 of 450B; [0105]) and an upper bonding pad (486 of 450B; [0105]) that electrically connect ([0107]) the transistor (450B) to the bit line (584 at 450B), wherein the lower bonding pad (586 of 450B) and the upper bonding pad (486 of 450B) are in contact with (connected to; [0107]) each other; and
a through via (996; [0121]) that electrically connects (power and/or electrical signals directly or indirectly for device operation; [0121]) the transistor (450B) to the connection conductive structure (998), wherein the transistor (450B), the upper bonding pad (486 of 450B), and the lower bonding pad (586 of 450B) overlap (partially cover) the memory cell structure (340 at 450B), and wherein the through via (996) penetrates ([0118] and [0121]) the upper substrate (430).
Re claim 3, Gan discloses the semiconductor device as claimed in claim 1, wherein the transistor (450B) overlaps (partially covers) the memory cell structure (340 at 450B).
Re claim 4, Gan discloses the semiconductor device as claimed in claim 1, wherein the transistor (450B) and the memory cell structure (340 at 450B) are electrically connected ([0107]) through the lower bonding pad (586 at 450B) and the upper bonding pad (486 at 450B).
Re claim 5, Gan discloses the semiconductor device as claimed in claim 1, wherein: the memory cell structure (340 at 450B) includes a bit line (584 at 450B; [0099]), the semiconductor device (3D memory 900) further includes a lower conductive structure (564/566; [0093]) that connects the bit line (584 at 450B) to the lower bonding pad (586 at 450B); and an upper conductive structure (462/464; [0093]) that connects the transistor (450B) to the upper bonding pad (486 at 450B).
Re claim 6, Gan discloses the semiconductor device as claimed in claim 1, wherein a bottom surface (lower plane) of the upper dielectric structure (upper 690) is bonded ([0103] and [0107]) to a top surface (upper plane) of the lower dielectric structure (lower 690).
Re claim 7, Gan discloses the semiconductor device as claimed in claim 1, wherein a level (vertical extension) of the memory cell structure (340 at 450B) is lower than (vertically below below) a level (vertical extension) of the upper bonding pad (486 at 450B) and a level (vertical extension) of the lower bonding pad (586 at 450B).
Re claim 8, Gan discloses the semiconductor device as claimed in claim 1, further comprising a through via (996; [0121]) that penetrates the upper substrate (430), wherein the through via (996) is electrically connected (for power and/or electrical signals directly or indirectly for device operation; [0121]) to the transistor (450B).
Re claim 10, Gan discloses the semiconductor device as claimed in claim 9, wherein the first upper bonding pad (486 at 450B) and the first lower bonding pad (586 at 450B) overlap (partially cover) the memory cell structure (340 at 450B).
Re claim 13, Gan discloses the semiconductor device as claimed in claim 9, further comprising: a connection structure (792/997/996; [0115] and [0121]-[0122]) that includes a connection dielectric structure (laminate 792/997; [0115] and [0122]) on the upper substrate (430) and a connection conductive structure (998; [0123]) in the connection dielectric structure (laminate 792/997); and a through via (996; [0121]) that electrically connects (power and/or electrical signals directly or indirectly for device operation; [0121]) the connection conductive structure (998) to the first transistor (450B),
wherein the through via (996) penetrates ([0118] and [0121]) the upper substrate (430).
Re claims 18-19, Gan discloses the semiconductor device as claimed in claim 9, wherein the memory cell structure (340 at 40B) includes bit lines (left/right 584 at 450B; [0099]; see inserted figure below) that extend in a first direction (Y; see inserted figure below) and are arranged in a second direction (X; see inserted figure below) that intersects (crosses) the first direction (Y), the first upper bonding pad (486 at 450B) includes two first upper bonding pads (left/right 486 at 450B; see inserted figure below) that are adjacent to (beside) each other in the first direction (Y), and the two first upper bonding pads (left/right 486 at 450B) are offset (separated; see inserted figure below) in the second direction (X); and wherein a pitch (separation; see inserted figure below) in the second direction (X) of the bit lines (left/right 584 at 450B) is the same as (equal to) an offset distance (separation; see inserted figure below) in the second direction (X) between the two first upper bonding pads (left/right 486 at 450B).
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For the record, the inserted figure (annotated FIG. 9 of Gan) depicts adjacent bit lines (left/right 584) and adjacent upper bonding pads (left/right 486) both extending in a first (Y) direction, and having the same (equal) pitch/offset (Off_BL and Off_UBP) at particular locations of the height of the adjacent bit lines (left/right 584) and the adjacent upper bonding pads (left/right 486).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2; and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Gan in view of Liu et al (US 2020/0279863 A1, hereafter Liu).
Re claim 2, Gan discloses the semiconductor device as claimed in claim 1.
But, fails to disclose wherein the transistor (450B) constitutes a sense amplifier.
However,
Liu discloses in FIG. 7 a semiconductor device (700) comprising: transistors (722; [0061]) configured as sense amplifiers ([0061]) in a second bonding structure (704).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gan by configuring the transistor as a sense amplifier among other peripheral devices, for facilitating the operation of the semiconductor device (Liu; [0061]).
Re claim 14, Gan discloses the semiconductor device as claimed in claim 13, wherein the upper bonding structure (400) includes: an upper contact (portion of 462; [0093]) connected to the first transistor (450B).
But, fails to disclose and an upper conductive line that connects the upper contact to the through via (996).
However, Liu discloses an upper conductive line (narrow unlabeled via below 728) that connects a first upper contact (wide unlabeled contact connected to narrow unlabeled via below 728) to a through via (728; [0062]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify the device of Gan by configuring an upper conductive line that connects the upper contact to the through via for direct transfer of electrical signals to the memory cell of the semiconductor device (Liu; [0062]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408)918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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/ERIC W JONES/Primary Examiner, Art Unit 2892