DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 5/22/2026. Claims 18-24, 26-32 & 34-37 are pending in this application. Claims 1-17, 25 & 33 are canceled.
Claim Objections
2. The claims are objected because of the following reasons:
Re claim 19-22: delete “Claim 17” and insert --Claim 18--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claims 18-22, 24, 26-29 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stamper et al. (US 2019/0172846).
Re claim 18, Stamper teaches, under BRI, Figs. 9-11, [0024, 0025, 0036], a semiconductor structure, comprising:
-a semiconductor substrate (102);
-a mesa stripe structure (indicated) on the semiconductor substrate (102), wherein the mesa stripe structure (indicated) comprises a plurality of alternating trenches (openings defined between 106c, 106a, 106b) and mesa stripes (106a, b as indicated) (Fig. 9); and
-a plurality of first contacts (145 or 145 with 120) on upper surfaces of a plurality of mesa stripes (106a, b as indicated) of the mesa stripe structure (indicated) other than a first mesa stripe (106c, 108, 133) of the mesa stripe structure (indicated) (Fig. 11), wherein the first mesa stripe (106c, 108, 133) comprises an oblique sidewall (indicated) and where the plurality of mesa stripes (106a, b) other than the first mesa stripes have vertical sidewalls (116);
wherein upper surfaces of the first mesa stripe (106c, 108, 133) are free of the first contacts (Fig. 11).
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Re claim 19, Stamper teaches, Fig. 3, wherein the first mesa stripe (106c, 108, 133) comprises an outermost one of the mesa stripes (indicated) (Fig. 9).
Re claim 20, Stamper teaches, under BRI, Fig. 11, wherein the first contacts (145 or 145 with 120) are formed on central portions of the mesa stripes (106a, b) other than the first mesa stripe (106c, 108, 133), and wherein end portions of the mesa stripes (106, b) (e.g., consider end sidewalls) are free of the first contacts.
Re claim 21, Stamper teaches, Fig. 10, a spacer (140) on an upper surface of the first stripe (106c, 108, 133), wherein mesa stripes (10a, b) other than the first mesa stripe (106c, 108, 133) are free of the spacer layer (140).
Re claim 22, Stamper teaches, Fig. 11, [0052], second contacts (additional devices 111) on bottom surfaces of the trenches (between 106a, 106c).
Re claim 24, Stamper teaches, under BRI, Figs. 9-11, [0022, 0024, 0025, 0030, 0036], a semiconductor transistor device structure, comprising:
-a semiconductor substrate (102);
-a mesa stripe structure (indicated) on the semiconductor substrate (102), wherein the mesa stripe structure (indicated) comprises a plurality of alternating trenches (openings defined between 106a, 106b, 106c) and mesa stripes (indicated) that define an active region of the transistor device structure [0030], wherein at least one mesa stripe (106c, 108, 133) of the mesa stripe structure is covered by a dielectric layer (140); and
-a plurality of contacts (145 or 145 with 120) on upper surfaces of a plurality of the mesa stripes (106a, b as indicated) of the mesa stripe structure other than the at least one mesa stripe (106c, 108, 133) of the mesa stripe structure;
wherein upper surfaces of the at least one mesa stripe (106c, 108, 133) are free of the contacts (Fig. 11)
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Re claim 26, Stamper teaches, Fig. 3, wherein the at least one mesa stripe (106c, 108, 133) comprises an outermost one of the mesa stripes (Fig. 9).
Re claim 27, Stamper teaches wherein the contacts (145 or 145 with 120) are formed on central portions of the mesa stripes (106a, b) other than the at least one mesa stripe (106c, 108, 133), and wherein end portions of the mesa stripes (106a, b) (e.g., consider end sidewalls) are free of the contacts (145 or 145 with 120).
Re claim 28, Stamper teaches, Fig. 10, a spacer layer (140) on an upper surface of the at least one mesa stripe (106c, 108, 133), wherein mesa stripes (106a, b) other than the at least one mesa stripe (106c, 108, 133) are free of the spacer layer (140).
Re claim 29, Stamper teaches, Fig. 11, [0052], second contacts (additional devices 111) on bottom surfaces of the trenches (Fig. 11).
Re claim 31, Stamper teaches, Fig. 10, wherein the at least one mesa stripe (106c, 108, 133) is entirely covered by a dielectric layer (140).
4. Claims 18-20, 22-24, 26, 27 and 29-31 are, alternatively, rejected under 35 U.S.C. 102(a)(1) as being anticipated by Odekirk et al. (US 8,519,410).
Re claim 18, Oderkirk teaches, under BRI, Fig. 8, pages 3-6, a semiconductor structure, comprising:
-a semiconductor substrate (SiC substrate 102);
-a mesa stripe structure (114 & indicated first mesa stripe) on the semiconductor substrate (SiC substrate 102), wherein the mesa stripe structure (114, & indicated first mesa stripe) comprises a plurality of alternating trenches (openings defined between 114) and mesa stripes (114); and
-a plurality of first contacts (124) on upper surfaces of a plurality of mesa stripes (left 114) of the mesa stripe structure (114 & indicated first mesa stripe) other than a first mesa stripe (indicated) of the mesa stripe structure (114 & indicated first mesa stripe), wherein the first mesa stripe (indicated) comprises an oblique sidewall (indicated) and where the plurality of mesa stripes (left 114) other than the first mesa stripes (indicated) have vertical sidewalls;
wherein upper surfaces of the first mesa stripe (indicated) are free of the first contacts (124).
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Re claim 19, Odekirk teaches, Fig. 8, wherein the first mesa stripe (indicated) comprises an outermost one of the mesa stripes.
Re claim 20, Odekirk teaches, Fig. 8, wherein the first contacts (124) are formed on central portions of the mesa stripes (left 114) (top view) other than the first mesa stripe, and wherein end portions of the mesa stripes (left 114) are free of the first contacts (124).
Re claims 22 & 23, Odekirk teaches, Fig. 8, a second contacts (126) on bottom surface of the trenches (between 114), wherein the first contacts (124) & the second contacts (126) are formed of a single metal layer.
Re claims 24 & 31, Odekirk teaches, under BRI, Fig. 8, abstract, pages 3-6, a semiconductor transistor device structure, comprising:
-a semiconductor substrate (102);
-a mesa stripe structure (114) on the semiconductor substrate (102), wherein the mesa stripe structure (114) comprises a plurality of alternating trenches (between 114) and mesa stripes (left 114) that define an active region (e.g., channel & gate regions) of the transistor device structure, wherein at least one mesa stripe (right 114) of the mesa stripe structure is covered by a dielectric layer (120), wherein the at least one mesa stripe (right 114) is entirely covered by the dielectric layer (120); and
-a plurality of contacts (124) on upper surfaces of a plurality of the mesa stripes (left 114) of the mesa stripe structure other than the at least one mesa stripe (right 114) of the mesa stripe structure;
wherein upper surfaces of the at least one mesa stripe (right 114) are free of the contacts (124).
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Re claim 26, Odekirk teaches, Fig. 8, wherein at least one mesa stripe (right 114) comprises an outermost one of the mesa stripes (114).
Re claim 27, Odekirk teaches, Fig. 8, wherein the contacts (124) are formed on central portions of the mesa stripes (left 114) (top view) other than the at least one mesa stripe (right 114), and wherein end portions (ends of left 114) of the mesa stripes are free of the contacts (124).
Re claims 29 & 30, Odekirk teaches, Fig. 8, second contacts (126) on bottom surfaces of the trenches (between 114); wherein the first contacts (124) and the second contacts (126) are formed form a single meta layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 23 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Stamper in view of Li et al. (US 2017/0133518).
The teachings of Stamper have been discussed above.
Re claims 23 & 30, Stamper teaches, Fig. 11, the first contacts (silicide 145) are formed from a single metal layer.
Stamper does not explicitly teach the second contacts are formed from a single metal layer.
Li teaches, Fig. 9, [0052], the second contacts (silicide 905) are formed from a single metal layer.
As taught by Li, one of ordinary skill in the art would utilize & modify the above teaching into Stamper to obtain the second contacts are formed from a single metal layer as claimed, because metal material is common and widely used as contacts in semiconductor devices and it aids in providing simplified process and reduced cost.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Li in combination with Stamper due to above reason.
6. Claims 32, 34 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Stamper et al. (US 2019/0172846) in view of Cheng et al. (US 2008/0124853).
Re claim 32, Stamper teaches, under BRI, Figs. 9-11, [0024, 0025, 0036], a semiconductor structure, comprising:
-a semiconductor substrate (102);
-a mesa stripe structure (indicated) on the semiconductor substrate (102), wherein the mesa stripe structure comprises a plurality of alternating trenches (opening defined between 106a, 106b, 106c) and mesa stripes (indicated), the mesa stripe structure comprising first outermost mesa stripe (106c, 108, 133) and a plurality of inner mesa stripes (indicated) (Fig. 9); and
-a plurality of first contacts (145) on upper surfaces of a plurality of mesa stripes (indicated) of the mesa stripe structure other than the first outermost mesa stripe (106c, 108, 133) of the mesa stripe structure (Fig. 11);
wherein upper surface of the first outermost mesa stripe (106c, 108, 133) is free of the first contacts (145) (Fig. 11); and
wherein the first contacts (145) are formed on central portions of the mesa stripes other than that first outermost mesa stripe (106a, 108, 133), wherein upper end surfaces of the mesa stripes are free of the first contacts (145) (Fig. 11).
Note: “on” # “physically on”.
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Stamper further teaches “FIG. 3 is not intended to be limiting and that process 12 can be performed so as to define any number of one or more semiconductor mesas” [0025], but does not explicitly teach a second outermost mesa stripe and the plurality of inner mesa strips between the first and second outermost mesa stripes; wherein upper surface of the second outermost mesa stripe is free of the first contacts.
Cheng teaches, Figs. 3 & 9A, a second outermost mesa stripe (6(a, b)) and the plurality of inner mesa strips (4, 5) between the first and second outermost mesa stripes (6(a, b)); wherein upper surface of the second outermost mesa stripe (6(a, b)) is free of the first contacts (13).
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As taught by Cheng, one of ordinary skill in the art would utilize & modify the above teaching into Stamper to obtain a second outermost mesa stripe and the plurality of inner mesa strips between the first and second outermost mesa stripes; wherein upper surface of the second outermost mesa stripe is free of the first contacts as claimed, because it aids achieving desired VJETs at low cost with precise control of channel length. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Cheng in combination with Stamper due to above reason.
Re claim 34, in combination cited above, Stamper teaches, Fig. 10, a spacer layer (140) on an upper surface of the first mesa stripe (106c, 108, 133), wherein mesa stripes (indicated) other than the first and second outermost mesa stripes are free of the spacer layer (140).
Re claim 37, in combination cited above, Cheng teaches, Figs. 3 & 9B, wherein the spacer (11) extends partially onto third and fourth mesa stripes (left 6b, right 6a) of the plurality of mesa stripes (4-7) adjacent to the first and second outermost mesa stripes (left 6a, right 6b).
7. Claims 35 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Stamper as modified by Cheng as applied to claims 32 above, and further in view of Li et al. (US 2017/0133518).
The teachings of Stamper/Cheng have been discussed above.
Re claims 35 & 36, Stamper/Cheng teaches the trenches and the first and second outermost mesa stripes (see claim 32 discussed above); wherein the first contacts (145) are formed from a single metal layer (see Stamper, Fig. 11).
Stamper/Cheng does not teach second contacts on bottom surfaces of the trenches except for trenches adjacent the first and second outermost mesa stripes; wherein the second contacts are formed from a single metal layer.
Li teaches, Fig. 17, second contacts (1705) on bottom surfaces of the trenches (in area 1701) except for trenches adjacent the first and second outermost mesa stripes (in area 1702); wherein the second contacts (1705) are formed from a single metal layer.
As taught by Li, one of ordinary skill in the art would utilize & modify the above teaching to obtain second contacts on bottom surfaces of the trenches except for trenches adjacent the first and second outermost mesa stripes; wherein the second contacts are formed from a single metal layer as claimed, because metal material is common and widely used as contacts in semiconductor devices and it aids in facilitating electrical connection by providing simplified process at reduced cost.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Li in combination with Stamper/Cheng due to above reason.
8. Claims 32 and 35-37 are, alternatively, rejected under 35 U.S.C. 103 as being unpatentable over Odekirk et al. (US 8,519,410) in view of Cheng et al. (US 2008/0124853).
Re claim 32, Odekirk teaches, under BRI, Fig. 8, pages 3-6, a semiconductor structure, comprising:
-a semiconductor substrate (102);
-a mesa stripe structure (114) on the semiconductor substrate (102), wherein the mesa stripe structure comprises a plurality of alternating trenches (between 114) and mesa stripes (left 114), the mesa stripe structure comprising first outermost mesa stripe (right 114) and a plurality of inner mesa stripes (middle 114); and
-a plurality of first contacts (124) on upper surfaces of a plurality of mesa stripes (left 114) of the mesa stripe structure other than the first outermost mesa stripe (right 114) of the mesa stripe structure;
wherein upper surface of the first outermost mesa stripe (right 114) is free of the first contacts (124); and
wherein the first contacts (124) are formed on (e.g., not physically on) central portions of the mesa stripes (left 114) (top view) other than that first outermost mesa stripe (right 114), wherein upper end surfaces of the mesa stripes (left 114) are free of the first contacts (124).
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Odekirk does not explicitly teach a second outermost mesa stripe and the plurality of inner mesa strips between the first and second outermost mesa stripes; wherein upper surface of the second outermost mesa stripe is free of the first contacts.
Cheng teaches, Figs. 3 & 9A, a second outermost mesa stripe (6(a, b)) and the plurality of inner mesa strips (4, 5) between the first and second outermost mesa stripes (6(a, b)); wherein upper surface of the second outermost mesa stripe (6(a, b)) is free of the first contacts (13).
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As taught by Cheng, one of ordinary skill in the art would utilize & modify the above teaching to obtain a second outermost mesa stripe and the plurality of inner mesa strips between the first and second outermost mesa stripes; wherein upper surface of the second outermost mesa stripe is free of the first contacts as claimed, because it aids achieving desired VJETs at low cost with precise control of channel length. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Cheng in combination with Odekirk due to above reason.
Re claims 35 & 36, in combination cited above, Odekirk teaches, Fig. 8, a second contacts (126) on bottom surfaces of the trenches except for trenches adjacent to the first and second outermost mesa stripes (consider (2x) right 114); wherein the first contacts (124) and the second contacts (126) are formed from a single metal layer.
Re claim 37, in combination cited above, Odekirk teaches, Fig. 8, wherein the spacer layer (120) extends partially only third and fourth stripes (middle 114) of the plurality of the mesa stripes adjacent to the first and second outermost mesa stripes (right 114) (based on more channels 148, col. 7, 4th par.).
Response to Arguments
9. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Applicant submits, in claim 18, “Stamper does not disclose or suggest a mesa stripe having an oblique sidewall that is free of metal contacts.
The examiner respectfully disagrees.
Under BRI and based on claimed language, as shown in Fig. 9, Stamper teaches mesa stripe (106c, 108, 133) having an oblique sidewall (defined from top of 106c to sidewall of 133), and contact 145 does not form on the mesa stripe (106a, 108, 133) (Fig. 11). Hence, Stamper meets the claimed invention.
Applicant submits, in claim 24, “the mesa 106c of Stamper is not part of a semiconductor device structure, and is not part of a mesa stripe structure that defines an active region of a semiconductor transistor”.
The examiner respectfully disagrees.
The claim does not require all mesa stripes of a mesa stripe structure that define an active region of a transistor device structure. Stamper teaches FETs 110a, b formed using semiconductor mesas 106a, 106b that match with the claimed requirement. Further, Stamper cites, [0030], “Specifically, the semiconductor mesa(s) 106a-106c could be used to form one or more active devices (e.g., field effect transistors (FETs), bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), etc.) and/or one or more passive devices (e.g., resistors, capacitors, diodes, etc.)”. Hence, mesa 106c can be a part of the mesa stripe structure that define an active region of a semiconductor transistor.
Applicant submits, in claim 32, “Neither Stamper nor Cheng shows end surfaces or end portions of a mesa stripe, and neither Stamper nor Cheng discloses or suggests at least the recitation "wherein the first contacts are formed on central portions of the mesa stripes other than the first and second outermost mesa stripes, and wherein upper end surfaces of the mesa stripes are free of the first contacts."
The examiner respectfully disagrees.
Indicated in Fig. 11 above and based on claimed language, Stamper teaches upper end surfaces (e.g., upper ends) of mesa stripes (indicated) are free of first contacts (145). In Fig. 11, Stamper teaches the first contacts (145) are formed on (# physically formed on) central portions of the mesa stripes (indicated) (top view of Fig. 11) other than a first outermost mesa stripe (106c, 108, 133). Cheng, in the other hand, teaches second outermost mesa (6a, b) is free of a contact (Fig. 9A). Hence, under BRI, Stamper/Cheng meet the claimed invention.
As result, given a broadest reasonable interpretation, Stamper or Stamper in view of Cheng meet all limitations cited in claims 18, 24 & 32.
Details included in the above rejection.
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/2/26
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