Prosecution Insights
Last updated: April 19, 2026
Application No. 18/370,995

PROTECTION OF MESA EDGES IN SEMICONDUCTOR DEVICES

Non-Final OA §102§103
Filed
Sep 21, 2023
Examiner
NGUYEN, DUY T V
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed, Inc.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
96%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
828 granted / 1052 resolved
+10.7% vs TC avg
Strong +17% interview lift
Without
With
+17.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
57 currently pending
Career history
1109
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
51.5%
+11.5% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
14.2%
-25.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1052 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Election/Restrictions 1. Applicant’s election without traverse of Group II, claims 18-31 in the reply filed on 1/15/2026 is acknowledged. Claims 18-37 are pending in this application. Claims 1-17 are cancelled. Claims 32-37 are new. Information Disclosure Statement 2. Applicant is suggested/reminded to disclose relevant prior art(s) or other information that may be material to the patentability of the invention in a pending application. The prior art information must be submitted in the form of an Information Disclosure Statement (“IDS”) (see MPEP 609 & 2001 and 37 CFR 1.56). Claim Objections 3. The claims are objected because of the following reasons: Re claim 25, line 4: in front of “mesa stripe”, delete “first” and insert --at least one--. Re claim 31, line 2: in front of “dielectric layer”, delete “a” and insert --the--, because “dielectric layer” is prior claimed. Re claim 32, -line 5: after “first and second outermost mesa”, delete “stripe” and insert –stripes--, -line 5: delete “strips” and insert --stripes--. Re claim 34, line 2: after “first”, insert --outermost--. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 4. Claims 18-22, 24-29 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stamper et al. (US 2019/0172846). Re claim 18, Stamper teaches, under BRI, Figs. 3-11, [0024, 0025, 0036], a semiconductor structure, comprising: -a semiconductor substrate (102); -a mesa stripe structure (mesas 106a-c, trenches 1911-4) on the semiconductor substrate (102), wherein the mesa stripe structure (106a-c, 1911-4) comprises a plurality of alternating trenches (1911-4) and mesa stripes (106a-c) (Fig. 3); and -a plurality of first contacts (145 or 145 & 120) on upper surfaces of a plurality of mesa stripes (106a-b) of the mesa stripe structure (106a-c, 1911-4) other than a first mesa stripe (106c) of the mesa stripe structure (106a-c, 1911-4) (Fig. 11); wherein upper surfaces of the first mesa stripe (106c) are free of the first contacts (Fig. 11). PNG media_image1.png 313 850 media_image1.png Greyscale Re claim 19, Stamper teaches, Fig. 3, wherein the first mesa stripe (106c) comprises an outermost one of the mesa stripes (106a-c) (Fig. 3). Re claim 20, Stamper teaches, under BRI, Fig. 11, wherein the first contacts (145 or 145 with 120) are formed on central portions of the mesa stripes (106a, b) other than the first mesa stripe (106c), and wherein end portions of the mesa stripes (106, b) (e.g., consider end sidewalls) are free of the first contacts. Re claim 21, Stamper teaches, Fig. 10, a spacer (140) on an upper surface of the first stripe (106c), wherein mesa stripes (10a, b) other than the first mesa stripe (106c) are free of the spacer layer (140). Re claim 22, Stamper teaches, Fig. 11, [0052], second contacts (additional devices 111) on bottom surfaces of the trenches (1911-4). Re claim 24, Stamper teaches, under BRI, Figs. 3-11, [0024, 0025, 0036], a semiconductor structure, comprising: -a semiconductor substrate (102); -a mesa stripe structure (mesas 106a-c, trenches 1911-4) on the semiconductor substrate (102), wherein the mesa stripe structure (106a-c, 1911-4) comprises a plurality of alternating trenches (1911-4) and mesa stripes (106a-c) (Fig. 3); wherein at least one mesa stripe (106c) of the mesa stripe structure is covered by a dielectric layer (140) (Fig. 10). PNG media_image2.png 283 869 media_image2.png Greyscale Re claim 25, Stamper teaches, under BRI, Fig. 11, a plurality of contacts (145 or 145 with 120) on upper surface of a plurality of mesa stripes (106a, b) of the mesa stripe structure (106a-c, 1911-4) other than the at least one mesa stripe (106c) of the mesa stripe structure; wherein upper surfaces of the first mesa stripe (106c) are free of the contacts. Re claim 26, Stamper teaches, Fig. 3, wherein the at least one mesa stripe (106c) comprises an outermost one of the mesa stripes (106a-c). Re claim 27, Stamper teaches wherein the contacts (145 or 145 with 120) are formed on central portions of the mesa stripes (106a, b) other than the at least one mesa stripe (106c), and wherein end portions of the mesa stripes (106a, b) (e.g., consider end sidewalls) are free of the contacts (145 or 145 with 120). Re claim 28, Stamper teaches, Fig. 10, a spacer layer (140) on an upper surface of the at least one mesa stripe (106c), wherein mesa stripes (106a, b) other than the at least one mesa stripe (106c) are free of the spacer layer (140). Re claim 29, Stamper teaches, Fig. 11, [0052], second contacts (additional devices 111) on bottom surfaces of the trenches (1911-4). Re claim 31, Stamper teaches, Fig. 10, wherein the at least one mesa stripe (106c) is entirely covered by a dielectric layer (140). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 5. Claims 23 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Stamper in view of Li et al. (US 2017/0133518). The teachings of Stamper have been discussed above. Re claims 23 & 30, Stamper teaches, Fig. 11, the first contacts (silicide 145) are formed from a single metal layer. Stamper does not explicitly teach the second contacts are formed from a single metal layer. Li teaches, Fig. 9, [0052], the second contacts (silicide 905) are formed from a single metal layer. As taught by Li, one of ordinary skill in the art would utilize & modify the above teaching into Stamper to obtain the second contacts are formed from a single metal layer as claimed, because metal material is common and widely used as contacts in semiconductor devices and it aids in providing simplified process and reduced cost. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Li in combination with Stamper due to above reason. 6. Claims 32-24 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Stamper et al. (US 2019/0172846) in view of Cheng et al. (US 2008/0124853). Re claim 32, Stamper teaches, under BRI, Figs. 3-11, [0024, 0025, 0036], a semiconductor structure, comprising: -a semiconductor substrate (102); -a mesa stripe structure (mesas 106a-c, trenches 1911-4) on the semiconductor substrate (102), wherein the mesa stripe structure (106a-c, 1911-4) comprises a plurality of alternating trenches (1911-4) and mesa stripes (106a-c), the mesa stripe structure comprising first outermost mesa stripe (106c) and a plurality of inner mesa strips (106a, b) (Fig. 3); and -a plurality of first contacts (145 or 145 with 120) on upper surfaces of a plurality of mesa stripes (106a, b) of the mesa stripe structure other than the first outermost mesa stripe (106c) of the mesa stripe structure (Fig. 11); wherein upper surface of the first outermost mesa stripe (106c) is free of the first contacts (145 or 145 with 120) (Fig. 11). PNG media_image1.png 313 850 media_image1.png Greyscale Stamper further teaches “FIG. 3 is not intended to be limiting and that process 12 can be performed so as to define any number of one or more semiconductor mesas” [0025], but does not explicitly teach a second outermost mesa stripe and the plurality of inner mesa strips between the first and second outermost mesa stripes; wherein upper surface of the second outermost mesa stripe is free of the first contacts. Cheng teaches, Figs. 3 & 9A, a second outermost mesa stripe (6(a, b)) and the plurality of inner mesa strips (4, 5) between the first and second outermost mesa stripes (6(a, b)); wherein upper surface of the second outermost mesa stripe (6(a, b)) is free of the first contacts (13). As taught by Cheng, one of ordinary skill in the art would utilize & modify the above teaching into Stamper to obtain a second outermost mesa stripe and the plurality of inner mesa strips between the first and second outermost mesa stripes; wherein upper surface of the second outermost mesa stripe is free of the first contacts as claimed, because it aids achieving desired VJETs at low cost with precise control of channel length. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Cheng in combination with Stamper due to above reason. Re claim 33, in combination cited above, Stamper teaches, under BRI, Fig. 11, wherein the first contacts (145 or 145 with 120) are formed on central portions of the mesa stripes (106a, b) other than the first and second outermost mesa stripes (106c) (see Cheng teaching above), and wherein end portions of the mesa stripes (106a, b) (consider end of sidewalls) are free of the first contacts (see also Cheng’s Fig. 9A). Re claim 34, in combination cited above, Stamper teaches, Fig. 10, a spacer layer (140) on an upper surface of the first mesa stripe (106c), wherein mesa stripes (106a, b) other than the first and second outermost mesa stripes are free of the spacer layer (140). Re claim 37, in combination cited above, Cheng teaches, Figs. 3 & 9B, wherein the spacer (11) extends partially onto third and fourth mesa stripes (left 6b, right 6a) of the plurality of mesa stripes (4-7) adjacent to the first and second outermost mesa stripes (left 6a, right 6b). 7. Claims 35 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Stamper as modified by Cheng as applied to claims 32 above, and further in view of Li et al. (US 2017/0133518). The teachings of Stamper/Cheng have been discussed above. Re claims 35 & 36, Stamper/Cheng teaches the trenches and the first and second outermost mesa stripes (see claim 32 discussed above); wherein the first contacts (145) are formed from a single metal layer (see Stamper, Fig. 11). Stamper/Cheng does not teach second contacts on bottom surfaces of the trenches except for trenches adjacent the first and second outermost mesa stripes; wherein the second contacts are formed from a single metal layer. Li teaches, Fig. 17, second contacts (1705) on bottom surfaces of the trenches (in area 1701) except for trenches adjacent the first and second outermost mesa stripes (in area 1702); wherein the second contacts (1705) are formed from a single metal layer. As taught by Li, one of ordinary skill in the art would utilize & modify the above teaching to obtain second contacts on bottom surfaces of the trenches except for trenches adjacent the first and second outermost mesa stripes; wherein the second contacts are formed from a single metal layer as claimed, because metal material is common and widely used as contacts in semiconductor devices and it aids in facilitating electrical connection by providing simplified process at reduced cost. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Li in combination with Stamper/Cheng due to above reason. Conclusion 8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY T NGUYEN/Primary Examiner, Art Unit 2818 1/30/26
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Prosecution Timeline

Sep 21, 2023
Application Filed
Feb 24, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
96%
With Interview (+17.1%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 1052 resolved cases by this examiner. Grant probability derived from career allow rate.

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