DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1- rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the phrase “original semiconductor surface” and it’s abbreviation “OSS” renders the claim indefinite because the claim includes elements not actually disclosed (those encompassed by “original semiconductor substrate”), thereby rendering the scope of the claim unascertainable. It should be noted that “original semiconductor substrate” does not have a clearly defined meaning, and seems to refer to semiconductor surfaces in general without specifying what makes it unique. The scope of the claim is unclear, and therefore the term is indefinite. For examination on the merits the limitation "original semiconductor surface" will be treated as a "semiconductor surface" since any "semiconductor surface" can be considered to be "original" on its own merit.
Regarding claims 2-7, they are dependent on claim 1 and thus rejected because they inherit the issue with the phrase “original semiconductor surface” and are indefinite.
Regarding claim 8, the phrase “original semiconductor surface” and it’s abbreviation “OSS” renders the claim indefinite because the claim includes elements not actually disclosed (those encompassed by “original semiconductor substrate”), thereby rendering the scope of the claim unascertainable. It should be noted that “original semiconductor substrate” does not have a clearly defined meaning, and seems to refer to semiconductor surfaces in general without specifying what makes it unique. The scope of the claim is unclear, and therefore the term is indefinite. For examination on the merits the limitation "original semiconductor surface" will be treated as a "semiconductor surface" since any "semiconductor surface" can be considered to be "original" on its own merit.
Regarding claims 9-14, they are dependent on claim 1 and thus rejected because they inherit the issue with the phrase “original semiconductor surface” and are indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kawabata et al. (US 7176080 B2) in view of Cheng et al. (US 7709320 B2).
Regarding claim 1, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 1, FIG. 2A, FIG. 2B, and FIG. 12 of Kawabata teaches a transistor structure (23, 24A; FIG. 1; column 3, lines 3-4) comprising:
a semiconductor substrate (22; FIG. 1; column 2, lines 60-61) with an original semiconductor surface (OSS) (35; FIG. 2A; FIG. 2B; column 3, lines 51-52);
a first gate region (36, 37; FIG. 2A; column 3, lines 60-61);
a first concave (26; FIG. 12; column3, lines 11-13) formed in the semiconductor substrate and below the original semiconductor surface; and
a first conductive region (29, 31; FIG. 12; column 3, lines 21-22, lines 31-33) formed in the first concave and including a first doping region (29, FIG. 12; column 3, lines 22-24) and a second doping region (31, FIG. 12; column 3, lines 33-35).
Kawabata et al. does not teach a curved or depressed shape opening formed along the vertical direction of a sidewall of the semiconductor substrate in the first concave; and
the first doping region being formed based on the curved or depressed shape opening along the vertical direction of the sidewall of the semiconductor substrate.
FIG. 1C and 3C of Cheng et al. teach a lower region (135C; FIG. 3C; column 6, lines 33-35) of trench (120C; FIG. 3C; column 6, lines 33-35) includes a vertical region (240; FIG. 3C; column 6, lines 33-35) and a bulbous region (245; FIG. 3C; column 6, lines 33-35) and that the trench (120; FIG. 1C; column 4, lines 34-36) is filled with a first electrically conductive fill material (160; FIG. 1C; column 4, lines 34-36), wherein in one example, the first fill material preferably comprises N-type doped polysilicon.
Kawabata et al. and Cheng et al. are both analogous to the claimed invention in that they involve transistor structures with trenches filled with doped material. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Kawabata et al. to have a curved or depressed shape opening formed along the vertical direction of a sidewall of the semiconductor substrate in the first concave and the first doping region being formed based on the curved or depressed shape opening along the vertical direction of the sidewall of the semiconductor substrate. This would serve the purpose of creating a “bottle trench capacitor” (column 6, lines 39-40).
Regarding claim 2, the combination of Kawabata et al. in view of Cheng et al. teaches the transistor structure according to claim 1. Kawabata et al. further teaches a top surface of the second doping region (31, FIG. 12; column 3, lines 33-35) being flat or planar.
Regarding claim 7, as best understood based on the 35 U.S.C. 112(b) issue identified above, the combination of Kawabata et al. in view of Cheng et al. teaches the transistor structure according to claim 1. Kawabata does not teach the curved or depressed shape opening being under the first gate region.
FIG. 2 and FIG. 3C of Cheng et al. further teach a gate electrode (205; FIG. 2; column 6, lines 4-7) located above where the bulbous area of the trench (245; FIG. 3C; column 6, lines 33-35) would be.
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Kawabata et al. to have the curved or depressed shape opening being under the first gate region. This allows for a field effect transistor to be built on the top surface of the substrate (column 2, lines 12-15).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kawabata et al. in view of Cheng et al. as applied to claim 1 above, and further in view of Hirler (US 20070108511 A1).
The combination of Kawabata et al in view of Cheng et al. teaches the transistor structure according to claim 1. Neither Kawabata et al. nor Cheng et al. teach the structure further comprising a metal plug contacting a top surface and a most lateral sidewall of the second doping region, wherein the second doping region is a heavily doped region.
FIG. 1A of Hirler teaches a metallization plug being used as field electrode material for a field electrode region (116; FIG. 1A; paragraph 0083), where it makes contact with a top surface and a sidewall of a heavily doped p+-region in the channel region (110; FIG. 1A; paragraph 0045)
Kawabata et al., Cheng et al., and Hirler are all analogous to the claimed invention in that they involve transistor structures with trench reasons. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to alter Kawabata to have a metal plug contacting a top surface and a most lateral sidewall of the second doping region, wherein the second doping region is a heavily doped region. That way, polysilicon deposition for forming the field electrode region can be omitted (paragraph 0083).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kawabata et al. in view of Cheng et al. as applied to claim 1 above, and further in view of Tailor et al. (US 20220093751 A1).
Regarding claim 6, as best understood based on the 35 U.S.C. 112(b) issue identified above, the combination of Kawabata et al. in view of Cheng et al. teach the transistor structure according to claim 1. Neither Kawabata et al. nor Cheng et al. teach the structure comprising a first isolation region in the first concave and the first conductive region being above the first isolation region.
FIG. 3 of Tailor et al. teaches Isolation region (108; FIG. 3; paragraph 0022) may be formed by etching a trench into the substrate (100; FIG. 3; paragraph 0022) and filling the trench with an insulating material to isolate one region of the substrate from as well as a conductive layer (118; FIG. 3; paragraph 0037) formed over the isolation region.
Kawabata et al., Cheng et al, and Tailor et al. are all analogous to the claimed invention in that they involve transistor structures with trenches. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have a first isolation region in the first concave and the first conductive region being above the first isolation region. This lengthens the current flow path, allowing for charge carrier mobility to be decreased and thereby reducing linear drain current (paragraph 0028).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cheng (US 20070189057 A1) concerns an integrated circuit connecting memory cells that includes transistors. Hummler (US 20030143809 A1) concerns a verticle gate transistor that includes a substrate and a trench..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
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/J.A.V./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817