Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed May 8th, 2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: The original disclosure lacks any mention of source and drain regions as part of the concave structure and including first and second doping regions. However, claims 1, 6, 8, and 10 feature the additions of source and drain regions in the concave and with the aforementioned multiple doping regions as part of the claimed invention. These are not mentioned in the specifications as part of the invention, and thus also violate 35 U.S.C 112(a).
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Objections
Claims 8 and 12 are objected to because of the following informalities:
Claim 8: the two instances of "curve and depress undercut" should .
Claim 12: the instance of “based on the another” should be “based on the other”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The amended claims 1, 6, 8, and 10 mention source and drain regions located in a concave and contain first and second doping regions. Only the source and drain regions are mentioned in the specifications, with no mention of them being a in a concave or having first.
Claims 2-7 are dependent on claim 1 and thus rejected.
Claims 9-14 are dependent on claim 8 and thus rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al.(US 20110042753 A1) in view of Bulucea et al. (US 20100244149 A1).
Regarding claim 1, FIG. 2A of Jain et al. teaches a transistor structure (paragraph 0015) comprising:
a semiconductor substrate (205; FIG. 2A; paragraph 0015; paragraph 0029) with a semiconductor surface (205; FIG. 2A; paragraph 0015; paragraph 0029);
a first gate region (215, 217; FIG. 2A; paragraph 0030);
a first concave (237; FIG. 2A; paragraph 0040) formed in the semiconductor substrate and below the original semiconductor surface;
a curved or depressed shape opening (237; FIG. 2A; paragraph 0040) formed along the vertical direction of a sidewall of the semiconductor substrate in the first concave; and
a source or drain (225, 230; FIG. 2A; paragraph 0031) in the first concave and including a first doping region (238; FIG. 2A; paragraph 0031);
wherein the first doping region is formed based on the curved or depressed shape opening along the vertical direction of the sidewall of the semiconductor substrate (FIG. 2A).
Jain et al. does not teach the transistor structure including a second doping region.
FIG. 11.1 of Bulucea et al. teaches a source (240; FIG. 11.1; paragraph 0363) with a heavily doped main portion (240M; FIG. 11.1; paragraph 0363) and a lightly doped extension (240E; FIG. 11.1; paragraph 0363).
Jain et al. and Bulucea et al. are both analogous with the claimed invention in that they involve semiconductor devices with semiconductor substrates and source and drain regions. Therefore, it would have been obvious for a person with ordinary skill in the art before the filing date of the claimed invention to modify Jain et al. so the source and drain regions have heavily and lightly doped regions. These are known aspects of source and drain regions (paragraph 0041).
Regarding claim 2, the combination of Jain et al. in view of Bulucea et al. teaches the transistor structure according to claim 1. Jain et al. does not teach the structure wherein a top surface of the second doping region is flat or planar.
FIG. 11.1 of Bulucea et al. teaches the lightly doped extension (240E; FIG. 11.1; paragraph 0363) of the source (240; FIG. 11.1; paragraph 0363) has a flat top.
It would have been obvious for a person with ordinary skill in the art before the filing date of the claimed invention to modify Jain et al. so the second doping region has a flat top. This is the result of the planar semiconductor surface (paragraph 0251).
Regarding claim 3, the combination of Jain et al. in view of Bulucea et al. teaches the transistor structure according to claim 1. FIG. 2A of Jain et al. further teaches the structure wherein the curved or depressed shape opening (237; FIG. 2A; paragraph 0040) is a sigma-shaped (E) undercut.
Regarding claim 5, the combination of Jain et al. in view of Bulucea et al. teaches the transistor structure according to claim 1. FIG. 2A of Jain et al. further teaches the structure wherein the curved or depressed shape opening (237; FIG. 2A; paragraph 0040) includes a plurality of non-vertical semiconductor segmental walls, and the first doping region (238; FIG. 2A; paragraph 0031) is selectively grown based on the plurality of non-vertical semiconductor segmental walls.
Regarding claim 7, the combination of Jain et al. in view of Bulucea et al. teaches the transistor structure according to claim 1. FIG. 2A of Jain et al. further teaches the structure wherein the curved or depressed shape opening (237; FIG. 2A; paragraph 0040) is under the first gate region (215, 217; FIG. 2A; paragraph 0030).
Claims 8, 11, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al. in view of Bulucea et al. as applied to claim 1 above, and further in view of Huang et al. (US 20210050247 A1).
Regarding claim 8, FIG. 3 of a first embodiment Jain et al. teaches a transistor structure (paragraph 0015) comprising:
a semiconductor substrate (205; FIG. 3; paragraph 0015; paragraph 0029) with a semiconductor surface (205; FIG. 3; paragraph 0015; paragraph 0029);
a first transistor (310; FIG. 3; paragraph 0015; paragraph 0036) comprising:
a first gate region (217(a); FIG. 3; paragraph 0036) over the semiconductor surface;
a first concave (232(a); FIG. 3; paragraph 0036) formed in the semiconductor substrate and below the semiconductor surface;
a first curved or depress undercut (232(a); FIG. 3; paragraph 0036) formed in the semiconductor substrate, below the first gate region and next to the first concave; and
a first source (225(a); FIG. 3; paragraph 0036) or a first drain (230(a); FIG. 3; paragraph 0036); and
a second transistor (320; FIG. 3; paragraph 0015; paragraph 0036) comprising:
a second gate region (217(b); FIG. 3; paragraph 0036) over the semiconductor surface;
a second concave (232(b); FIG. 3; paragraph 0036) formed in the semiconductor substrate and below the semiconductor surface;
a second curved or depress undercut (232(a); FIG. 3; paragraph 0036) formed in the semiconductor substrate, below the second gate region and next to the second concave; and
a second source (225(b); FIG. 3; paragraph 0036) or a second drain (230(a); FIG. 3; paragraph 0036).
Jain et al. does not teach with a first doping region and a second doping region in the first source or first drain; wherein at least portion of the first doping region is within the first curved or depress undercut; and a third doping region and a fourth doping region within the second source and second drain; wherein at least portion of the third doping region is within the second curved or depress undercut.
FIG. 11.1 of Bulucea et al. teaches a source (240; FIG. 11.1; paragraph 0363) with a heavily n-type doped main portion (240M; FIG. 11.1; paragraph 0363) and a lightly n-type doped extension (240E; FIG. 11.1; paragraph 0363) near an n-type gate (262; FIG. 11.1; paragraph 00362) as well as a second source (280; FIG. 11.1; paragraph 0445) with a heavily p-type doped main portion (280M; FIG. 11.1; paragraph 0445) and a lightly p-type doped extension (280E; FIG. 11.1; paragraph 0445) near an p-type gate (302; FIG. 11.1; paragraph 00444). Bulucea et al. does not teach at least a portion of the first doping region being within the first curved or depress undercut and at least a portion.
FIG. 17A of Huang et al. teaches a drain/source region (1704; FIG. 17A; paragraph 0053) with a concave filled with n-type dopants and a drain/source region (1706; FIG. 17A; paragraph 0053) with a concave filled with p-type dopants.
Jain et al., Bulucea et al., and Huang et al. are all analogous with the claimed invention in that they involve semiconductor devices with semiconductor substrates and source and drain regions. Therefore, it would have been obvious for a person with ordinary skill in the art before the filing date of the claimed invention to modify Jain et al. so the source and drain regions have heavily and lightly doped regions n-type and p-type regions that fill the depressed shapes in concave structures. These are known aspects of source and drain regions (Bulcea et al.: paragraph 0041) and are the result doping the whole source/drain region (Huang et al.: paragraph 0053).
Regarding claim 11, the combination of Jain et al. in view of Bulucea et al. and further in view of Huang et al. teaches the transistor structure according to claim 8. Jain et al. does not teach the structure wherein a top surface of the second doping region is flat or planar, and a top surface of the fourth doping regions is flat or planar.
FIG. 11.1 of Bulucea et al. teaches both the lightly doped extension (240E; FIG. 11.1; paragraph 0363) of the n-type source (240; FIG. 11.1; paragraph 0363) and the lightly doped extension (280E; FIG. 11.1; paragraph 0445) of the p-type source (280; FIG. 11.1; paragraph 0445) have flat tops.
It would have been obvious for a person with ordinary skill in the art before the filing date of the claimed invention to modify Jain et al. so the second doping region has a flat top. This is the result of the planar semiconductor surface (paragraph 0251).
Regarding claim 12, the combination of Jain et al. in view of Bulucea et al. and further in view of Huang et al. teaches the transistor structure according to claim 8. Jain et al. does not teach the structure wherein the first curved or depressed undercut includes a plurality of non-vertical semiconductor segmental walls, and the first doping region is selectively grown based on the plurality of non-vertical semiconductor segmental walls;
wherein the second curved or depressed undercut includes another plurality of non-vertical semiconductor segmental walls, and third doping region is selectively grown based on the another plurality of non-vertical semiconductor segmental walls.
FIG. 17A of Huang et al. teaches a first drain/source region (1704; FIG. 17A; paragraph 0053) with a depressed area carved into the side walls of the semiconductor fins (212; FIG 17A; paragraph 0020) as non-vertical segments filled with n-type dopants and a drain/source region (1706; FIG. 17A; paragraph 0053) with a depressed area carved into the side walls of the semiconductor fins (212; FIG 17A; paragraph 0020) as non-vertical segments filled with p-type dopants.
It would have been obvious for a person with ordinary skill in the art before the filing date of the claimed invention to modify Jain et al. so that the depressed areas were non-vertical segmental walls filled the first and third doping regions. This is a known way to cut the region and the result of doping the whole source/drain region (Huang et al.: paragraph 0053).
Regarding claim 14, the combination of Jain et al. in view of Bulucea et al. and further in view of Huang et al. teaches the transistor structure according to claim 8. Jain et al. does not teach the structure wherein a doping concentration of the second doped region is the same or substantially the same as that of fourth doping region.
FIG. 11.1 of Bulucea et al. teaches a lightly doped extension (240E; FIG. 11.1; paragraph 0363) of the n-type source (240; FIG. 11.1; paragraph 0363) and a lightly doped extension (280E; FIG. 11.1; paragraph 0445) of the p-type source (280; FIG. 11.1; paragraph 0445).
It would have been obvious for a person with ordinary skill in the art before the filing date of the claimed invention to modify Jain et al. so the second and fourth doping areas had the substantially the same concentration. This allows both regions to function for the same purpose allowing the source/drain regions to function properly by reducing hot carrier injection into the gate (paragraph 0040).
Response to Arguments
Applicant’s arguments rely, filed May 8th, 2026, rely on an amendment objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: The original disclosure lacks any mention of source and drain regions as part of the concave structure and including first and second doping regions. However, claims 1, 6, 8, and 10 feature the additions of source and drain regions.
Examiner has examined the claims as currently amended to the best ability.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kawabata et al. (US 7176080 B2) concerns a semiconductor device with trenches in active areas. Chen et al. (US 20070275510 A1) concerns a MOSFET device with source/drain extensions formed in trenches.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB ALEXANDER VLCEK/ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
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