Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20100200898-A1 referred as Lin) in view of Jo et al. (US-20220165834-A1 referred as Jo).
Regarding claim 1. Lin discloses semiconductor package comprising:
a package substrate ([0097], figure 3c, a package substrate #34);
a semiconductor chip on the package substrate ([0039], figure 3c, the semiconductor chip #1 as illustrated. Please note the semiconductor chip #1 consists of multiple elements including #2 - #5, #17, #18 and #19 all interconnected as one element);
a transparent substrate on the semiconductor chip ([0107], figure 3c, the transparent substrate #11 is seen on the semiconductor chip #1);
a dam structure between the semiconductor chip and the transparent substrate ([0096], figure 3c, the dam structure #25 is seen in between the semiconductor chip #1 and the transparent substrate #11);
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a dummy pad on a lower side of the dam structure and to which no wiring is connected ([0048], figure 3E annotated above, the chip pad #19 consists of a dummy pad #19b which has no wire connected to it and is on the lower side of the dam structure #25);
a planarization film extending along an upper surface of the semiconductor chip ([0050], figure 3c, the planarization film #6 extending along an upper surface of the semiconductor chip #1); and
a passivation film on the planarization film and spaced apart from the dam structure ([0058], figure 3c, the passivation film #20 is on the planarization film #6 and spaced apart from the dam structure #25).
Lin lacks the planarization film spaced apart from the dam structure; and the passivation film surrounding a side surface of the planarization film and extending to and under the dam structure.
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Figure 6 Flipped
Jo discloses the planarization film spaced apart from the dam structure ([0088], figure 6 flipped and annotated above, the planarization film #OC is seen spaced apart from the dam structure #ILD); and the passivation film surrounding a side surface of the planarization film and extending to and under the dam structure ([0088], figure 6 flipped and annotated above, the passivation film #PAS is seen surrounding a side surface of the planarization film #OC at the reference #Th while also extending to and under the dam structure #ILD).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin to include the passivation film surrounding a side surface of the planarization film and extending to and under the dam structure as taught by Jo in order to provide additional electrical insulation, distribute the weight across the device, and to extend the devices lifetime.
Regarding claim 3. Lin as modified discloses further comprising a chip pad outside the dummy pad and on the lower side of the dam structure ([0090], figure 3e annotated above, a chip pad (#19, and #21) outside the dummy pad #19b and on the lower side of the dam structure #25),
wherein the package substrate comprises a substrate pad ([0098], figure 3c, the package substrate #34 consists of substrate pads #40),
wherein the substrate pad and the chip pad are connected to each other by a wire ([0102], figure 3c, the substrate pad #40 and the chip pad (#19, and #21) are connected to each other by a wire (#42, #24, and #22). Please note the wire #42 is conductive to the metals #24 and #22 which allows for continuity from the chip pad (#19, #21) to the substrate pad #40), and
wherein the dummy pad is not connected to the substrate pad (figure 3e annotated above, the dummy pad #19b is not connected to the substrate pad #40).
Regarding claim 7. Lin as modified discloses further comprising a mold layer on the package substrate, the mold layer covering side surfaces of each of the semiconductor chip, the dam structure, and the transparent substrate ([0105], figure 3c, a mold layer #43 on the package substrate #34 covering the side surfaces of the semiconductor chip #1, the dam structure #22 and the transparent substrate #11).
Regarding claim 8. Lin as modified discloses wherein the dummy pad completely overlaps the dam structure (see annotated figure 3E above, dummy pad 19B completely overlaps dam structure 25 – meaning if looking at the figure in the horizontal direction dam structure 25 fully covers dummy pad 19b, therefore broadly ‘completely overlaps’ in a horizontal direction).
Regarding claim 9. Lin as modified discloses wherein a portion of the dummy pad does not overlap the dam structure (see annotated figure 3E above, all of dummy pad 19B does not overlap dam structure 25 in the vertical direction, therefore, since the whole element does not overlap in the vertical direction ‘a portion’ would also not overlap, thus reading on the broad claim language – think of rotating the figure 90 degrees when looking for ‘overlap’).
Claims 6 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20100200898-A1 referred as Lin) and Jo et al. (US-20220165834-A1 referred as Jo) in view of Guo et al (US-20220155612-A1 referred as Guo).
Regarding claim 6. Lin as modified discloses wherein the semiconductor chip comprises an image sensor chip comprising a color filter and a micro lens, and wherein the planarization film is on a lower side of the micro lens on the color filter ([abstract] [0107], figure 3c, the semiconductor chip #1 which uses image sensor components as described contains a color filter #7 and a microlens #8, wherein the planarization film #6 is on the lower side of the microlens #8 on the color filter #7).
Lin lacks wherein the passivation film is on the micro lens.
Guo discloses wherein the passivation film is on the micro lens ([0069], figure 8, the passivation film #28 is on the microlens #27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin to include the passivation film is on the micro lens. as taught by Guo in order to enhance protection to the lenses, increase the devices lifetime, and to provide additional clarity to the devices image output.
Regarding claim 20. Lin discloses a semiconductor package comprising:
a package substrate comprising a plurality of substrate pads ([0105], figure 3c, a package substrate #34 comprising of substrate pads #40);
an image sensor chip on the package substrate ([abstract], [0039], figure 3e, the semiconductor substrate #1 is tailored for image sensor devices as what the invention describes in the abstract, therefore the semiconductor substrate is the image sensor chip #1. Also, the image sensor chip #1 consists of multiple elements including #2 - #5, #17, #18 and #19 all interconnected as one element. The image sensor chip #1 is seen on the package substrate #40);
a plurality of chip pads on an upper surface of the image sensor chip ([0105], figure 3c, chip pads #19 on the upper surface of the image sensor chip #1);
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a dummy pad on the upper surface of the image sensor chip, wherein a distance from the dummy pad to a central portion of the image sensor chip is smaller than a distance from the plurality of chip pads to the central portion ([0048], figure 3e annotated above, the dummy pad #19b on the upper surface of the image sensor chip #1. The distance from the dummy pad #19b to the central position is closer than the distance from the chip pads #19 to the central position);
a dam structure on the plurality of chip pads and the dummy pad ([0105], figure 3c, the dam structure #25 is on the chip pads #19 and the dummy pad #19b); and
a transparent substrate on the image sensor chip and the dam structure ([0105], figure 3c, a transparent substrate #11 on the image sensor chip #1 and the dam structure #25),
wherein the image sensor chip comprises: a plurality of micro lenses ([0105], figure 3c, the image sensor chip #1 consists of a microlenses #8);
a planarization film on a lower side of the plurality of micro lenses ([0105], figure 3c, a planarization film #20 on the lower side of the microlens #8); and
wherein the planarization film is spaced apart from the dam structure ([0105], figure 3c, the planarization film #20 is spaced apart from the dam structure #25),
wherein the plurality of chip pads and the plurality of substrate pads are connected to each other by bonding wires ([0105], figure 3c, the chip pads #19 and the substrate pad #40 are connected by bonding wires #42. please not the conductivity from the bonding wire #42 reaches to the chip pads #19 through the conductivity of the metals #24, #22, and #21), and
wherein the dummy pad and the plurality of substrate pads are not connected to each other ([0105], figure 3c, the dummy pad #19b and the substrate pads #19 are not connected to each other).
Lin lacks a passivation film covering the plurality of micro lenses, wherein the passivation film covers a side surface of the planarization film and extending to and under the dam structure.
Guo discloses a passivation film covering the plurality of micro lenses ([0069], figure 8, a passivation film #28 covering the microlens #27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin to include a passivation film covering the plurality of micro lenses as taught by Guo in order to enhance protection to the lenses, increase the stability of the lenses, and to provide additional integrity in the device.
Lin as modified by Guo still lacks wherein the passivation film covers a side surface of the planarization film and extends to and under a lower side of the dam structure.
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Figure 6 Flipped
Jo discloses wherein the passivation film covers a side surface of the planarization film and extends to and under the dam structure ([0088], figure 6 flipped and annotated above, the passivation film #PAS is seen covering a side surface of the planarization film #OC at the reference #Th which also extends to and under the dam structure #ILD as seen with the flipped figure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified by Guo to include wherein the passivation film covers a side surface of the planarization film and extends to a lower side of the dam structure as taught by Jo in order to provide additional electrical insulation, distribute the weight across the device, and to extend the devices lifetime.
Regarding claim 21. Lin as modified discloses wherein the passivation film extends beyond the planarization film such that a portion of the passivation film contacts the dummy pad ([0039], figure 3e annotated above, the passivation film #6 extends beyond the planarization film #20 and has a portion contacting the dummy pad #19b).
Regarding claim 22. Lin as modified discloses wherein the passivation film extends beyond the planarization film such that a portion of the passivation film is between the dam structure and the dummy pad ([0039], figure 3e annotated above, the passivation film #6 extends beyond the planarization film #20 and has a portion in between the dam structure #25 and the dummy pad #19b).
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20100200898-A1 referred as Lin) and Jo et al. (US-20220165834-A1 referred as Jo), in view of Kang et al. (US-20120153498-A1).
Regarding claim 4. Lin as modified discloses wherein the chip pad is in contact with the dam structure ([0089], figure 3c, the chip pad (#19, #21) is in contact with the dam structure #25).
Lin as modified lacks wherein the chip pad is exposed from the passivation film.
Kang et al. discloses wherein the chip pad is exposed from the passivation film ([0080], figure 18, the chip pad #39a is exposed from the passivation film #19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin to include the chip pad being exposed from the passivation film as taught by Kang et al. in order to reduce latency, enhance device compactness, reduce overall use of material in manufacturing.
Regarding claim 10. as modified lacks wherein the passivation film covers an entire upper surface of the dummy pad.
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Kang et al. discloses wherein the passivation film covers an entire upper surface of the dummy pad ([0080], figure 18 annotated above, the passivation film #19 covers an entire upper surface of the dummy pad #39b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin to include the passivation film covering an entire upper surface of the dummy pad as taught by Kang et al. in order to enhance electrical protection, increase device integrity, and to increase the devices lifetime.
Claims 11-12, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20100200898-A1 referred as Lin), in view of Kang et al. (US-20180040658-A1 referred as Kang).
Regarding claim 11. Lin discloses A semiconductor package comprising:
a package substrate ([0097], figure 3c, a package substrate #34);
an image sensor chip on the package substrate, the image sensor chip comprising a plurality of micro lenses at a central portion of the image sensor chip ([abstract], [0039], figure 3e, the semiconductor substrate #1 is tailored for image sensor devices as what the invention describes in the abstract, therefore the semiconductor substrate is the image sensor chip #1. Also, the image sensor chip #1 consists of multiple elements including #2 - #5, #17, #18 and #19 all interconnected as one element. The image sensor chip #1 comprises of microlenses #8 at a central point of the image sensor chip #1);
a plurality of chip pads on an upper surface of the image sensor chip ([0090], figure 3c, the plurality of chip pads #19 are on an upper surface of the image sensor chip #1);
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a dummy pad on the upper surface of the image sensor chip, wherein a distance from the dummy pad to the central portion is smaller than a distance from the plurality of chip pads to the central portion ([0048], figure 3e annotated above, the dummy pad #19b on the upper surface of the image sensor chip #1. The distance from the dummy pad #19b to the central position is closer than the distance from the chip pads #19 to the central position);
a dam structure on the plurality of chip pads and the dummy pad, the dam structure surrounding the central portion ([0096, figure 3c, a dam structure #25 on the plurality of chip pads #19 and dummy pads #19b and also surrounding the central portion);
a transparent substrate on the image sensor chip and the dam structure ([0107], figure 3c, a transparent substrate #11 on the image sensor chip #1 and the dam structure #25); and
a plurality of substrate pads on an upper surface of the package substrate and surrounding the image sensor chip ([0102], figure 3c, a plurality of substrate pads #40 on an upper surface of the package substrate #34 and surrounding the image sensor chip #1),
wherein the plurality of chip pads and the plurality of substrate pads are connected to each other by bonding wires ([0102], figure 3c, the chip pads #19 and the substrate pads #40 are connected each other by bonding wires #42, #24, #22, and #21. Please not the conductivity from the bonding wire #42 reaches to the chip pads #19 through the conductivity of the metals #24, #22, and #21), and
wherein the dummy pad and the plurality of substrate pads are not connected to each other (figure 3c, the dummy pad #19b and the substrate pad #40 are not connected to each other).
Lin lacks wherein the dummy pad entirely surrounds the central portion of the image sensor chip. Kang discloses wherein the dummy pad entirely surrounds the central portion of the image sensor chip ([0050], figure 2B, the dummy pads #202 entirely surrounds the central portion of the image sensor chip #500).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin to include the dummy pad entirely surrounds the central portion of the image sensor chip as taught by Kang in order to provide electrical consistency in the device, distribute the weight of the structure, and to provide additional protection to the circuit.
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Regarding claim 12. Lin as modified discloses wherein an upper surface of the dummy pad, upper surfaces of the plurality of chip pads, and the upper surface of the image sensor chip are on a same plane ([0107], figure 3e annotated above, the upper surface of the dummy pad #19b, chip pads #19, and the image sensor chip #1 (more specifically on top of sublayer #5 labeled as #5-surface in figure 1a annotated above) are all on the same plane).
Regarding claim 17. Lin as modified discloses wherein the plurality of chip pads and the dummy pad comprise a same material ([0050], figure 3c, the chip pads #19 and the dummy pad #19b comprise of the same material).
Regarding claim 19. Lin as modified discloses wherein the dam structure covers an entire upper surface of the dummy pad (see annotated figure above as to figure 3E, dam structure 25 cover the entire upper surface of dummy pad 19b, meaning if you were looking down at the figure from above, dam structure 25 would fully cover dummy pad 19b).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20100200898-A1 referred as Lin), in view of Kang et al. (US-20180040658-A1 referred as Kang), in further view of Kang et al. (US-20120153498-A1 referred as Kang #2).
Regarding claim 13. Lin as modified discloses wherein the image sensor chip further comprises:
a planarization film on a lower side of the plurality of micro lenses ([0058], figure 3c, a planarization film #20 on the lower side of the microlenses #8), and
wherein the planarization film does not overlap the dam structure ([0058], figure 3c, the planarization film #20 does not overlap the dam structure #25).
Lin as modified lacks a passivation film on the plurality of micro lenses.
Kang #2 discloses a passivation film on the plurality of micro lenses ([0075], figure 9, a passivation film #28 on the plurality of microlenses #27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to include a passivation film on the plurality of micro lenses as taught by Kang #2 in order to enhance protection to the lenses, increase the stability of the lenses, and to provide additional integrity in the device.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20100200898-A1 referred as Lin), Kang et al. (US-20180040658-A1 referred as Kang), and (US-20120153498-A1 referred as Kang #2) as applied to claim 13 in further view of Lin et al. (US-20110051390-A1 referred as Lin #2).
Regarding claim 14. Lin as modified lacks wherein the passivation film comprises: a first extension portion covering the planarization film, a second extension portion extending from a side portion of the planarization film to a lower side of the dam structure, and a vertical portion connecting the first extension portion to the second extension portion, wherein the vertical portion is spaced apart from the dam structure.
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Lin #2 discloses wherein the passivation film comprises: a first extension portion covering the planarization film ([0017], figure 2a, the passivation film #224 is seen covering the planarization film #222 as seen in first extension portion #1EP), a second extension portion extending from a side portion of the planarization film to a lower side of the dam structure ([0017], figure 2a, the passivation film #224 extending from the side portion of the planarization film #222 to a lower side of the dam structure #210 as seen in second extension portion #2EP), and a vertical portion connecting the first extension portion to the second extension portion, wherein the vertical portion is spaced apart from the dam structure ([0017], figure 2a, a vertical portion #VP connecting the first extension portion #1EP to the second extension portion #2EP wherein the vertical portion #VP is spaced apart from the dam structure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to include a particular coverage from the passivation film on to the planarization film in reference to the dam structure as taught by Lin #2 in order to provide consistent electrical protection to the circuit, reduce short circuits, and to improve safety.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20100200898-A1 referred as Lin), Kang et al. (US-20180040658-A1 referred as Kang), and Kang et al. (US-20120153498-A1 referred as Kang #2) and Lin et al. (US-20110051390-A1 referred as Lin #2) as applied to claim 15, in further view of Oh et al. (US-20190295986-A1).
Regarding claim 15. Lin as modified lacks wherein the second extension portion exposes a portion of upper surfaces of the plurality of chip pads to which the bonding wires are connected.
Oh et al. discloses wherein the second extension portion exposes a portion of upper surfaces of the plurality of chip pads to which the bonding wires are connected ([0034], figure 3, the passivation layer #211 contains a second extension portion which exposes a portion of the upper surfaces of the chip pads #209 to which the bonding wires #230 are connected to).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to include the passivation layer having an opening for the chip pads as taught by Lin #2 in order to reduce electrical latency, improve circuit performance, and to reduce materials in manufacturing.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20100200898-A1 referred as Lin), and Kang et al. (US-20180040658-A1 referred as Kang), in further view of Jang et al. (US-20180123222-A1).
Regarding claim 16. Lin as modified lacks wherein the dummy pad has a quadrangular ring shape exposing the central portion.
Jang et al. discloses wherein the dummy pad has a quadrangular ring shape exposing the central portion ([claim 11], [0102], figure 6, the dummy pad #190 has a quadrangular ring shape with an empty exposed central portion).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to include the dummy pad has a quadrangular ring shape as taught by Jang et al. discloses in order to reduce materials in manufacturing, provide a consistent connectivity throughout, and to reduce the weight of the device.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20100200898-A1 referred as Lin) and Kang et al. (US-20180040658-A1 referred as Kang) in view of Lee et al. (US-20090262226-A1 referred as Lee).
Regarding claim 18. Lin as modified lacks wherein a width of the dummy pad is greater than a width of the plurality of chip pads.
Lee discloses wherein a width of the dummy pad is greater than a width of the plurality of chip pads ([0014], figure 1, the width of the dummy pad #42 is greater than the width of the chip pads #302.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to include wherein the width of the dummy pad is greater than a width of the chip pads as taught by Lee in order to distribute weight evenly across the device, and increase the versatility of the device.
Response to Amendment
Applicant's arguments filed 03/09/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art by new prior art. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
For claims 1 and 20 regarding pages 9-10 and 13 of the Remarks ... "Applicant's amendments and arguments were persuasive. Upon further search and consideration a new rejection using a new interpretation of Lin et al. in combination with newly cited reference to Jo et al. has been presented with regard to claims 1 and 20, including a different interpretation of Gau in combination for claim 20.
For claim 11 regarding page 12 of the Remarks .... "Applicant's amendments and arguments were persuasive. Upon further search and consideration a new rejection using a different interpretation of Lin et al. in combination with newly cited reference to Kang et al. has been presented with regard to claims 11."
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818