DETAILED ACTION
The Applicant Arguments/Remarks (of RCE) filed March 02, 2026 has been entered. Claims 1-18 are pending. Claims 1 and 10 are independent.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 10-16 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Singh et al. (US 2017/0186483) in view of e.g., Sharma et al. (US 2011/0305099).
Regarding independent claim 1 and its method independent claim 10, Singh et al. teach a memory (e.g., FIGS. 1-2) comprising:
a memory array (100), comprising:
a plurality of wordlines (WLs);
a plurality of bitlines (BLs), comprising:
a first bitline (e.g., 120), routed on a first metal layer (METAL0- BL) but not a second metal layer (METAL1); and
a second bitline (e.g., 124), routed on the first metal layer (METAL0-BL) and the second metal layer (MTAL1), wherein the second metal layer is different from the first metal layer (see FIGS. 1-2 and accompanying disclosure, e.g., paras. 0041-0044); and a plurality of memory cells, each coupled to one of the plurality of wordlines (see FIGS. 1-2), wherein the plurality of memory cells comprise:
a first group of memory cells (110), coupled to the first bitline; and
a second group of memory cells (108), coupled to the second bitline, wherein the first group of memory cells and the second group of memory cells are located at a same column (see e.g., FIGS. 1-2 and accompanying disclosure; and a single-ended sense amplifier circuit (I/O), arranged to perform a read operation upon a target memory cell through single-ended sensing when a selected wordline is enabled, wherein the target memory cell is selected from the first group of memory cells and the second group of memory cells (see e.g., FIGS. 1-2 and accompanying disclosure).
Singh et al’ I/O circuits including sense amplifier for data reading does not explicitly disclose a single-ended SA circuit, fully implemented in a global input/output (I/O) circuit of the memory and arranged to perform a read operation upon a target memory cell through single-ended sensing when a selected wordline is enabled, wherein the target memory cell is selected from the first group of memory cells and the second group of memory cells, and the single-ended sensing performed by the single-ended sense amplifier circuit comprises receiving a first single-ended input signal from the first bitline and a second single-ended input signal from the second bitline, and performing a logic operation upon the first single-ended input signal and the second single-ended input signal.
However, claimed a single-ended SA circuit, fully implemented in a global input/output (I/O) circuit in a memory array is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Sharma et al. teach the deficiencies in e.g., FIGS. 5-7, the shared read buffer 17 (i.e., claimed single SA) fully implemented in global I/O area (see GRBL 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Sharma et al. to the teaching of Singh et al. such that a memory, as taught by Singh et al., utilizes a single-ended SA, as taught by Sharma et al., for the purpose of enhancing data read operation and reducing data I/O area, further these conventional technology are well established in the art of the memory devices.
Regarding claims 2 and 11, Singh et al., and Sharma et al., as combined, teach the limitations 1 and 10, respectively.
Sharma et al. further teach each memory cell included in the first group of memory cells and the second group of memory cells employs a single-port static random access memory (SRAM) cell architecture (FIG. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Sharma et al. for the same purpose of extension of enhancing memory operations.
Regarding claims 3 and 12, Singh et al., and Sharma et al., as combined, teach the limitations 1 and 10, respectively.
Singh et al. further teach each memory cell included in the first group of memory cells and the second group of memory cells employs a two-port static random access memory (SRAM) cell architecture (FIGS. 3A-B).
Regarding claims 4 and 13, Singh et al., and Sharma et al., as combined, teach the limitations 1 and 10, respectively.
Sharma et al. further teach the single-ended sense amplifier circuit comprises: a logic gate circuit, comprising: a first input node, coupled to the first bitline; a second input node, coupled to the second bitline; and an output node; and an output latch circuit, comprising: an input node, coupled to the output node of the logic gate circuit; and an output node, arranged to output a read-out data of the target memory cell (FIGS. 5-7).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Sharma et al. for the purpose of enhancing data read operation and reducing data I/O area, further these conventional technology are well established in the art of the memory devices.
Regarding claims 5 and 14, Singh et al., and Sharma et al., as combined, teach the limitations 4 and 13, respectively.
Sharma et al. further teach the logic gate circuit is a NAND gate (FIG. 5).
Regarding claims 6 and 15, Singh et al., and Sharma et al., as combined, teach the limitations 4 and 13, respectively.
Singh et al. further teach the first bitline is one of two bitlines of one complementary bitline pair, and the second bitline is one of two bitlines of another complementary bitline pair (FIG. 1).
Regarding claims 7 and 16, Singh et al., and Sharma et al., as combined, teach the limitations 4 and 13, respectively.
Singh et al. further teach the first bitline is one read bitline, the second bitline is another read bitline, and none of the first bitline and the second bitline is used by a write operation (FIG. 1, further read bit line is dedicated read memory operation is an inherent memory characteristic).
Claims 8-9 and 17-18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Singh et al. (US 2017/0186483) in view of Sharma et al. (US 2011/0305099), further in view of Augustine et al. (US 2023/0284427).
Regarding claims 8-9 and 17-18, Singh et al., and Sharma et al., as combined, teach the limitations 1 and 10, respectively.
Singh et al. do not explicitly disclose a cell number of the first group of memory cells is different from a cell number of the second group of memory cells; and the cell number of the first group of memory cells is larger than the cell number of the second group of memory cells.
Augustine et al. teach the deficiencies in e.g., FIG. 14B.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Augustine et al. to the teaching of Singh et al. and Sharma et al., as combined, such that a memory, as taught by Singh et al. and Sharma et al., utilizes different group of memory array, as taught by Augustine et al., for the purpose of utilizing lowered capacitance to accommodate more cells in the BLs routed (see Augustine, paragraph [0103]), therefore enhancing memory array utilization.
Response to Argument
Applicant’s Arguments/Remarks filed 03/02/2026, with respect to the rejection(s) of claims, has been fully considered but are not persuasive.
For a compact prosecution, the examiner points out and answers the main features of the applicant’s argument.
Applicant argues that the shared read buffer 17 (in Sharma’s figures 5-7) is not a sense amplifier. Shama’s sense amplifier is designated as a 21 in figure 1 and is a differential sense amplifier. So, Sharma fails to teach or suggest the claimed limitation “ a single-ended sense amplifier circuit, fully implemented in a global input/output (I/O) circuit”.
In response to the applicant’s arguments, the shared read buffer 17 (NAND gate) is a sense amplifier. A sense amplifier is a circuit (component) that reads small signal from storage (memory cells) and amplifies them into strong, readable voltage levels such as large signal, “0” and “1”. A single-ended sense amplifier is sense amplifier connected to one data line (bit line), rather than a differential sense amplifier. For example, an “inverter”1 is a single-ended sense amplifier. A “NAND gate”2 or a “NOR gate” is also a single-ended sense amplifier. Therefore, Sharma’s shared read buffer - NAND gate - is presented as a single-ended sense amplifier that reads a small signal on a single bit line (just over threshold voltage) and amplifies it into the logical signals “0” and “1”. A NAND gate single-ended sense amplifier is also described in the Applicant’s figure 1, 112.
In the art rejection above, the examiner mentioned claimed “a single-ended SA circuit, fully implemented in a global input/output (I/O) circuit of a memory” is a well-known technology for a type of memory for its purpose. For a compact prosecution, the examiner presents additional references supporting the aforementioned facts.
Lee (US 2011/0199839), FIG. 2 and para. 0021: … the single ended sense amplifier 106 …
Lee et al. (US 2018/0151211), FIG. 6: 130, and para. 0038: … In some embodiments, the sense amplifier 130 is a differential sense amplifier. In other embodiments, the sense amplifier 130 is a single ended sense amplifier.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
1 See, for example, Sharma et al. (US 2024/0389292), figure 2 and accompanying disclosure, e.g., paragraph [0046]: … a simple single-ended sense amplifier such as inverters …; Siddiqui et al. (US 2020/0219558), figure 9 and accompanying disclosure, … sense inverter 930 …
2 See, for example, Lu et al. (US 2018/0367318), figure 4 and accompanying disclosure, e.g., paragraph [0030]: … a single-ended sense amplifier made out of a NAND logic gate 250 …
Prosecution Insights