DETAILED ACTION
The RCE filed October 14, 2026 has been entered. Claims 1-18 are pending. Claims 4 and 13 have been cancelled. Claims 1 and 10 are independent.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, 10-12 and 14-16 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Singh et al. (US 2017/0186483) in view of e.g., Sharma et al. (US 2011/0305099) and Takami (US 2009/0251980).
Regarding independent claim 1 and its method independent claim 10, Singh et al. teach a memory (e.g., FIGS. 1-2) comprising:
a memory array (100), comprising:
a plurality of wordlines (WLs);
a plurality of bitlines (BLs), comprising:
a first bitline (e.g., 120), routed on a first metal layer (METAL0- BL) but not a second metal layer (METAL1); and
a second bitline (e.g., 124), routed on the first metal layer (METAL0-BL) and the second metal layer (MTAL1), wherein the second metal layer is different from the first metal layer (see FIGS. 1-2 and accompanying disclosure, e.g., paras. 0041-0044); and a plurality of memory cells, each coupled to one of the plurality of wordlines (see FIGS. 1-2), wherein the plurality of memory cells comprise:
a first group of memory cells (110), coupled to the first bitline; and
a second group of memory cells (108), coupled to the second bitline, wherein the first group of memory cells and the second group of memory cells are located at a same column (see e.g., FIGS. 1-2 and accompanying disclosure; and a single-ended sense amplifier circuit (I/O), arranged to perform a read operation upon a target memory cell through single-ended sensing when a selected wordline is enabled, wherein the target memory cell is selected from the first group of memory cells and the second group of memory cells (see e.g., FIGS. 1-2 and accompanying disclosure).
Singh et al’ I/O circuits including sense amplifier for data reading does not explicitly disclose claimed a single-ended sense amplifier circuit and an output latched circuit.
However, claimed a single-ended SA circuit, fully implemented in a global input/output (I/O) circuit in a memory array; and an output latched circuit is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example1, Sharma et al. teach the deficiencies, i.e., a single-ended sense amplifier circuit (e.g., FIGS. 5-7, the shared read buffer 17), fully implemented in a global input/output(I/O) circuit (see GRBL 5, here, G stands for global) of the memory and arranged to perform a read operation upon a target memory cell through single-ended sensing when a selected wordline is enabled (e.g., FIG. 2, WL, along with FIG. 5), wherein the target memory cell is selected from the first group of memory cells (e.g., FIG. 5: Cell <0:7>) and the second group of memory cells (Cell <8:15>), and the single-ended sense amplifier circuit comprises; a logic gate circuit (e.g., FIG. 5: 17), having a first input node (one input of NAND), a second input node (the other input of NAND), and an output node (NAND output), wherein the first input node is arranged to receive receiving a first single-ended input signal from the first bitline during the read operation (RBL, R stands for read), the second input node is arranged to receive a second single-ended input signal from the second bitline during the read operation (see e.g., FIG. 5), and the logic gate circuit, fully implemented in the global I/O circuit (Global BL, G stands for global), is arranged to perform the single-ended sensing by performing a logic operation upon the first single-ended input signal and the second single-ended input signal, and generate an output signal at the output node of the logic gate circuit (see e.g., FIG. 5 and accompanying disclosure).
Takami teaches the deficiencies, i.e., an output latch circuit (e.g., FIG. 1: 110), having an input node (SAout) and an output node (Data-Out), wherein the input node of the output latch circuit is directly connected to the output node of the logic gate circuit (see FIG. 1), and the output latch circuit, fully implemented in the global I/O circuit (see FIG. 5: I/O), is arranged to output a read-out data of the target memory cell at the output node of the output latch circuit (see 1-6: 110 and accompanying disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Sharma et al. and Takami to the teaching of Singh et al. such that a memory, as taught by Singh et al., utilizes a single-ended SA and output latch, as taught by Sharma et al. and Takami, for the purpose of enhancing data read operation and reducing data I/O area, further these conventional technology are well established in the art of the memory devices.
Regarding claims 2 and 11, Singh et al., Sharma et al. and Takami, as combined, teach the limitations 1 and 10, respectively.
Sharma et al. further teach each memory cell included in the first group of memory cells and the second group of memory cells employs a single-port static random access memory (SRAM) cell architecture (FIG. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Sharma et al. for the same purpose of extension of enhancing memory operations.
Regarding claims 3 and 12, Singh et al., Sharma et al. and Takami, as combined, teach the limitations 1 and 10, respectively.
Singh et al. further teach each memory cell included in the first group of memory cells and the second group of memory cells employs a two-port static random access memory (SRAM) cell architecture (FIGS. 3A-B).
Regarding claims 5 and 14, Singh et al., Sharma et al. and Takami, as combined, teach the limitations 1 and 10, respectively.
Sharma et al. further teach the logic gate circuit is a NAND gate (FIG. 5).
Regarding claims 6 and 15, Singh et al., Sharma et al. and Takami, as combined, teach the limitations 1 and 10, respectively.
Singh et al. further teach the first bitline is one of two bitlines of one complementary bitline pair, and the second bitline is one of two bitlines of another complementary bitline pair (FIG. 1).
Regarding claims 7 and 16, Singh et al., Sharma et al. and Takami, as combined, teach the limitations 1 and 10, respectively.
Singh et al. further teach the first bitline is one read bitline, the second bitline is another read bitline, and none of the first bitline and the second bitline is used by a write operation (FIG. 1, further read bit line is dedicated read memory operation is an inherent memory characteristic).
Claims 8-9 and 17-18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Singh et al. (US 2017/0186483) in view of Sharma et al. (US 2011/0305099) and Takami (US 2009/0251980), further in view of Augustine et al. (US 2023/0284427).
Regarding claims 8-9 and 17-18, Singh et al., Sharma et al. and Takami, as combined, teach the limitations 1 and 10, respectively.
Singh et al. do not explicitly disclose a cell number of the first group of memory cells is different from a cell number of the second group of memory cells; and the cell number of the first group of memory cells is larger than the cell number of the second group of memory cells.
Augustine et al. teach the deficiencies in e.g., FIG. 14B.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Augustine et al. to the teaching of Singh et al. and Sharma et al., as combined, such that a memory, as taught by Singh et al. and Sharma et al., utilizes different group of memory array, as taught by Augustine et al., for the purpose of utilizing lowered capacitance to accommodate more cells in the BLs routed (see Augustine, paragraph [0103]), therefore enhancing memory array utilization.
Response to Argument
Applicant’s RCE filed 08/14/2026, with respect to the rejection(s) of claims, has been fully considered but are moot in view of the new ground(s) of rejection.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1Further, see, for example, Sharma et al. (US 2024/0389292), figure 2 and accompanying disclosure, e.g., paragraph [0046]: … a simple single-ended sense amplifier such as inverters …; Siddiqui et al. (US 2020/0219558), figure 9 and accompanying disclosure, … sense inverter 930 …
See, for example, Lu et al. (US 2018/0367318), figure 4 and accompanying disclosure, e.g., paragraph [0030]: … a single-ended sense amplifier made out of a NAND logic gate 250 …
See, for example, Lee (US 2011/0199839), FIG. 2 and para. 0021: … the single ended sense amplifier 106 …
See, for example, Lee et al. (US 2018/0151211), FIG. 6: 130, and para. 0038: … In some embodiments, the sense amplifier 130 is a differential sense amplifier. In other embodiments, the sense amplifier 130 is a single ended sense amplifier.
Prosecution Insights