Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “intrinsic” in claims 1 and 10 is a relative term which renders the claim indefinite. The term “intrinsic” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Because the term “intrinsic” does not clearly add to or mean anything specific regarding the gap of the semiconductor device and is not defined in the spec, the scope of claims 1 and 10 is unclear. For examination purposes, the term “intrinsic” has been omitted. Claims 2-9 and 11-15 are also rejected based solely on their dependency.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 102(a)1 as being anticipated by Mendez et al. ("Quantum Transport Simulations for Si:P δ-layer Tunnel Junctions" See attached NPL).
Regarding Claim 1, Mendez teaches a semiconductor device having first and second conductivity regimes, comprising:
a substrate body (Mendez, fig. 2, substrate body labeled Si Body (see annotated figure below));
a source formed along a first sidewall of the substrate body (Mendez, fig. 2, Source (structure labeled Source) formed along a first sidewall (left sidewall) of the substrate body);
a drain formed along a second sidewall of the substrate body (Mendez, fig. 2, Drain (structure labeled drain) formed along a second sidewall (right sidewall) of the substrate body);
first and second delta layers disposed on the substrate body and separated by a gap forming a delta-layer tunnel junction for direct tunneling transport, wherein the first delta layer is in contact with the source and the second delta layer is in contact with the drain (Fig. 2, first and second delta layers attached to the source and drain (see annotated figure below), and disposed on the substrate body and separated by an intrinsic gap W. This arrangement supports direct tunneling transport (See the Results and Discussion section);
and a cap disposed over the first and second delta layers (Fig. 2, cap (labeled Si cap) disposed over the first and second delta layers),
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wherein the semiconductor device has the first conductivity regime responsive to a first voltage between the drain and the source and has the second conductivity regime responsive to a second voltage between the drain and the source (Fig. 3b teaches the device operating under a plurality of voltages (for example, a first voltage is 0.105 V, and a second voltage may be 0.135 V) and displaying exponential growth as the tunnel gap increases. As best understood by the examiner, from Applicant’s own specification (paragraph 0036) and Drawings (fig. 3), this exponential trend is indicative of two conductivity regimes: a low and high-conductivity regime).
Regarding Claim 2, Mendez teaches the semiconductor device of claim 1, wherein the second voltage is higher than the first voltage (Fig. 3b teaches the device can be operated such that the first voltage can be 0.105 V, and the second voltage can be 0.135 V. Therefore, the second voltage is higher than a second voltage).
Regarding Claim 3, Mendez teaches the semiconductor device of claim 1, wherein a current between the drain and the source is higher in the second conductivity regime than a current between the drain and the source in the first conductivity regime (As best understood by the examiner, from Applicant’s own specification (paragraph 0036) and drawings (fig. 4), the first conductivity regime occurs when the applied voltage is at or below 0.05 V, and the second conductivity regime occurs when the voltage is at or above 0.08 V. Fig. 3a of Mendez teaches a current vs. applied voltage graph with respect to the gap length. Therefore, at a gap length of 8 nm, the second conductivity regime (when the applied village is at or above 0.08 V) demonstrates higher currents than currents in the first conductivity regime (when the applied voltage is at or below 0.05 V).
Regarding Claim 4, Mendez teaches the semiconductor device of claim 1, wherein the first voltage is between 0 V and 0.05 V, and wherein the second voltage is between 0.075 V and 0.11 V (Fig. 3b teaches a first voltage of 0.045 V, and a second voltage of 0.105 V).
Regarding Claim 5, Mendez teaches the semiconductor device of claim 1, wherein the first and second delta layers are embedded between the substrate body and the cap (Fig. 2 and the first paragraph of the cited NPL reference teaches the first and second delta layers are embedded between the substrate body and the cap).
Regarding Claim 6, Mendez teaches the semiconductor device of claim 1, wherein the first and second delta layers are formed by thin layers of phosphorus (Paragraph 1 of the Results And Discussion section teaches that the channel embedded in the substrate body is formed of thin layers of Phosphorous (P δ-layer) with a thickness t).
Regarding Claim 7, Mendez teaches the semiconductor device of claim 1, wherein the substrate body and the cap are formed of a semiconductor material (Paragraph 1 of the Results And Discussion section teaches that the substrate body and the cap are formed of the semiconductor material Silicon).
Regarding Claim 8, Mendez teaches the semiconductor device of claim 1, wherein the first delta layer extends from the source into a region between the substrate body and the cap, and wherein the second delta layer extends from the drain into another region between the substrate body and the cap (See fig. 2).
Regarding Claim 9, Mendez teaches the semiconductor device of claim 1, wherein the gap separating the two delta layers is between 2 nano-meters and 12 nano-meters (Fig. 3a teaches the device having a gap between 0 nm and 15 nm, which includes the claimed gap width range).
Regarding Claim 10, Mendez teaches a semiconductor device having first and second resistive states, comprising:
a substrate body (Mendez, fig. 2, substrate body labeled Si Body (see annotated figure below));
a source formed along a first sidewall of the substrate body (Mendez, fig. 2, Source (structure labeled Source) formed along a first sidewall (left sidewall) of the substrate body);
a drain formed along a second sidewall of the substrate body (Mendez, fig. 2, Drain (structure labeled drain) formed along a second sidewall (right sidewall) of the substrate body);
first and second delta layers disposed on the substrate body and separated by a gap forming a delta-layer tunnel junction for direct tunneling transport, wherein the first delta layer is in contact with the source and the second delta layer is in contact with the drain (Fig. 2, first and second delta layers attached to the source and drain (see annotated figure below), and disposed on the substrate body and separated by an intrinsic gap W. This arrangement supports direct tunneling transport (See the Results and Discussion section);
and a cap disposed over the first and second delta layers (Fig. 2, cap (labeled Si cap) disposed over the first and second delta layers),
wherein the semiconductor device has the first resistive state responsive to a first voltage between the drain and the source and has the second resistive state responsive to a second voltage between the drain and the source Fig. 3b teaches the device operating under a plurality of voltages (for example, a first voltage is 0.105 V, and a second voltage may be 0.135 V) and displaying exponential growth as the tunnel gap increases. As best understood by the examiner, from Applicant’s own specification (paragraph 0036) and Drawings (fig. 3), this exponential trend is indicative of two conductivity regimes: a low and high-conductivity regime. Further, Applicant’s own specification (paragraph 0017) teaches that if the semiconductor device has two conductivity regimes, the device also has two resistivity states. Therefore, the device a first resistive state responsive to a first voltage (0.105 V) and a second resistive state responsive to a second voltage (0.135 V)).
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Regarding Claim 11, Mendez teaches the semiconductor device of claim 10, wherein the semiconductor device has a first resistance in the first resistive state and has a second resistance in the second resistive state (Paragraph 0017 of applicant’s own specification teaches that because the semiconductor device has two conductivity regimes, the device also has two resistive states. Therefore, since Mendez teaches a semiconductor device having first and second conductivity regimes responsive to first and second voltages, it also teaches that the device has first and second resistive states responsive to first and second voltages. Further, the semiconductor device has a first resistance in the first resistive state and a second resistance in the second resistive state).
Regarding Claim 12, Mendez teaches the semiconductor device of claim 11, wherein the first resistance is higher than the second resistance (Paragraph 0017 of applicant’s own specification teaches because the semiconductor device has two conductivity regimes, the device also has two resistive states and that the first resistance is higher than the second resistance. Therefore, because the semiconductor device taught Mendez is of the same structure and has two conductivity regimes, the device also has two resistive states and the first resistance is higher than the second resistance).
Regarding Claim 13, Mendez teaches the semiconductor device of claim 10, wherein the second voltage is higher than the first voltage (Fig. 3b teaches a first voltage of 0.045 V, and a second voltage of 0.105 V, therefore the second voltage is higher than the first voltage).
Regarding Claim 14, Mendez teaches the semiconductor device of claim 10, wherein the first voltage is between 0 V and 0.05 V, and wherein the second voltage is between 0.075V and 0.11 V (Fig. 3b teaches a first voltage of 0.045 V, and a second voltage of 0.105 V).
Regarding Claim 15, Mendez teaches the semiconductor device of claim 10, wherein the first and second delta layers are formed by thin layers of phosphorus Paragraph 1 of the Results and Discussion section teaches that the channel embedded in the substrate body is formed of thin layers of Phosphorous (P δ-layer) with a thickness t).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot in view of the new grounds of rejection as applied above.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure. Applicant(s) is/are directed to consider additional pertinent prior art on the Notice of References Cited (PTO-892) attached herewith.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICENTE R GONZALES whose telephone number is (571)272-3365. The examiner can normally be reached Monday - Friday 7:30 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/V.R.G./
Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
