Prosecution Insights
Last updated: October 27, 2026

Vicente Rolando Gonzales, USPTO Patent Examiner

Listed by the USPTO as GONZALES, VICENTE ROLANDO

Tech Center 2800 • Art Units: 2893 2899

This examiner grants 100% of resolved cases

Analysis

Vicente Rolando Gonzales has a limited history with only 3 resolved cases in Art Unit 2893. All 3 cases resulted in an allowance, yielding a 100.0 percent allowance rate. The median days to allowance for these files is 1015. With an interview lift of 0.0 percent, there is no data yet to suggest that interviews change the outcome for applicants like Samsung Electronics Co., Ltd. Firms such as Harrity & Harrity, LLP should note that while the 100.0 percent rate is perfect, it is based on a very small sample size. The 1015-day timeline provides a preliminary benchmark for pendency in this art unit.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

100.0%
Allow Rate
+32.0% vs TC avg
38
Total Applications
+0.0%
Interview Lift
1015
Avg Prosecution Days
Based on 3 resolved cases, 2023–2026

Rejection Statute Breakdown

0%
§101 Eligibility
27.0%
§102 Novelty
57.0%
§103 Obviousness
14.0%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18826635 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18807028 SEMICONDUCTOR PACKAGE Non-Final OA Samsung Electronics Co., Ltd.
18772412 SEMICONDUCTOR PACKAGE Non-Final OA Samsung Electronics Co., Ltd.
18492181 MAGNETIC MEMORY DEVICES USING SPIN CURRENT AND ELECTRONIC APPARATUSES INCLUDING THE MAGNETIC MEMORY DEVICES Non-Final OA Samsung Electronics Co., Ltd.
18529154 LIGHT EMITTING DISPLAY APPARATUS Final Rejection LG Display Co., Ltd.
18368016 DISPLAY DEVICE Non-Final OA Samsung Display Co., Ltd.
18705532 Display Substrate, Preparation Method Therefor, and Display Apparatus Non-Final OA BOE Technology Group Co., Ltd.
18279398 DISPLAY APPARATUS, AND DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR Final Rejection BOE Technology Group Co., Ltd.
18193295 INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING METAL POSTS THERMALLY COUPLING A DIE TO AN INTERPOSER SUBSTRATE FOR DISSIPATING THERMAL ENERGY OF THE DIE, AND RELATED FABRICATION METHODS Non-Final OA QUALCOMM Incorporated
18567796 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Non-Final OA Mitsubishi Electric Corporation
18067207 HEAT DISSIPATION STRUCTURES FOR BONDED WAFERS Final Rejection INTERNATIONAL BUSINESS MACHINES CORPORATION
18081795 STACKED VERTICAL-TRANSPORT FIELD EFFECT TRANSISTORS (VTFETs) Final Rejection INTERNATIONAL BUSINESS MACHINES CORPORATION
18465598 POWER SEMICONDUCTOR DEVICE, MEASUREMENT SYSTEM AND METHOD FOR DETERMINING A CURRENT OF A POWER SEMICONDUCTOR DEVICE Non-Final OA Infineon Technologies AG
18790083 SEMICONDUCTOR DEVICE Non-Final OA ROHM CO., LTD.
18646458 ADHESION OF A PACKAGE COMPONENT TO A HEAT SINK Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18368014 SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME Final Rejection TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
18406543 SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING Non-Final OA Taiwan Semiconductor Manufacturing Company Limited
18371160 TWO DIMENSIONAL SEMICONDUCTOR TRANSISTOR, TWO DIMENSIONAL SEMICONDUCTOR WITH THE SAME AND MANUFACTURING METHOD THEREOF Final Rejection KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
18826849 REPAIR TECHNIQUES FOR MICRO-LED DEVICES AND ARRAYS Non-Final OA VueReal Inc.
18488376 SEMICONDUCTOR POWER DEVICE WITH IMPROVED JUNCTION TERMINATION EXTENSION Non-Final OA NEXPERIA B.V.
18815693 MANUFACTURING METHOD OF ELECTRONIC PACKAGE Non-Final OA SILICONWARE PRECISION INDUSTRIES CO., LTD.

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Frequently Asked Questions

What is examiner Vicente Rolando Gonzales's allowance rate?

100.0% of resolved applications examined by Vicente Rolando Gonzales were allowed (3 resolved cases), compared with 79.0% across Art Unit 2893 over the last five years.

Does an interview help with examiner Vicente Rolando Gonzales?

This examiner's interview lift is +0.0 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.

How long does examiner Vicente Rolando Gonzales take to allow a patent?

Applications allowed by Vicente Rolando Gonzales took 1,015 days on average from filing to allowance.

Which art unit does examiner Vicente Rolando Gonzales work in?

Vicente Rolando Gonzales examines applications in Art Unit 2893 in Tech Center 2800 (Semiconductors, Circuits & Optics).

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