DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 3/25/2026. Claims 1-6 are pending in this application.
Claim Objections
2. The claims are objected because of the following reasons:
Re claim 5, line 1: a preamble states “A base-side semiconductor chip comprising” is objected because the claim includes “a bonding-side semiconductor chip” which is another chip different from “a base-side semiconductor chip”.
Re claim 6, line 1: a preamble states “A bonding-side semiconductor chip comprising” is objected because the claim includes “a base-side semiconductor chip” which is another chip different from “a bonding-side semiconductor chip”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komuta et al. (US 2013/0250298) in view of Morita (US 2008/0211086).
Re claim 1, Komuta teaches, under BRI, Figs. 1-4, 8 & 9A-B, [0041-0042], a semiconductor device comprising:
-a first semiconductor chip (10-1) on which a first alignment mark (left 11a), a second alignment mark (right 11a), first and second terminals (12) for measuring conduction (*), are disposed; and
-a second semiconductor chip (10-2) on which a third alignment mark (left 11b), a fourth alignment mark (right 11b), are disposed; and which is bonded to the first semiconductor chip (10-1) such that the first alignment mark (left 11a) and the third alignment mark overlap (left 11b), and the second alignment mark (right 11a) and the fourth alignment mark overlap (right 11b),
wherein, in a state in which the second semiconductor chip (10-2) is bonded to the first semiconductor chip (10-1) such that the first alignment mask (left 11a) overlaps the third alignment mark (left 11b) and the second alignment mark (right 11a) overlaps the fourth alignment mark (right 11b).
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Komuta does not explicitly teach a first wiring that electrically connects the first alignment mark and the first terminal, and a second wiring that electrically connects the second alignment mark and the second terminal; and a third wiring that electrically connects the third alignment mark and the fourth alignment mark, and the third wiring electrically connects the first alignment mark and the second alignment mark to each other.
Morita teaches, Figs. 11 & 17, [0010, 0063, 0084, 0090] & based on semiconductor devices, a first wiring (consider 251) that electrically connects the first alignment mark (left 230) and the first terminal (left 221), and a second wiring (251) that electrically connects the second alignment mark (right 230) and the second terminal (right 221) (Fig. 11); a third wiring (260) that electrically connects the third alignment mark (left 230) and the fourth alignment mark (right 230); and the third wiring (260) electrically connects the first alignment mark and the second alignment mark (consider left & right portions of 252 contacting with 230) to each other (Fig. 17).
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As taught Morita, one of ordinary skill in the art would utilize & modify the above teaching to obtain first, second & third wirings, and the third wiring electrically connects the first alignment marks and the second alignment marks to each other as claimed, because it aids in improving the connection stability & improving the device performance. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Morita in combination with Komuta due to above reason.
(*) The limitation “…for measuring conduction” is merely a functional/intended use limitation that does not structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114. Additionally, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Re claim 2, Komuta teaches, [0041], the first alignment mark (left 11a), the second alignment mark (right 11a), the third alignment mark (left 11b), and the fourth alignment mark (right 11b) are different in shape (e.g., different shapes) from a connection terminal for connecting the first semiconductor chip (10-1) and the second semiconductor chip (10-2) to each other.
Re claim 3, Komuta teaches, Fig. 6A, the first terminal (12) and the second terminal (12) are smaller in dimension than other terminals (13) required for operation of the semiconductor device.
Re claim 4, in combination cited above, Morita teaches, under BRI, Fig. 17, the third wiring (consider 260) that electrically connects the third alignment mark and the fourth alignment mark is arranged outside (e.g., above) a semiconductor element region of the second semiconductor chip (semiconductor device 220).
Re claim 5, Komuta teaches, under BRI, Figs. 6A & 9A, [0041-0042], a base-side semiconductor chip (10-1) comprising:
-a plurality of base-side alignment marks (11a); and
-measurement terminals (electrode 12) for measuring conduction (as intended use or based on conductive material) (*); and
wherein the measurement terminals (12) are configured to measure conduction (as intended use or based on conductive material) (*) in a case where a bonding-side semiconductor chip (10-2) is bonded such that the base-side alignment marks (11a) and a plurality of bonding-side alignment marks (11b) provided on the bonding-side semiconductor chip (10-2) overlap, and wherein, in a state in which the bonding side semiconductor chip (10-2) is bonded to the base-side semiconductor chip (10-1) such that the base-side alignment mark (11a) overlap the bonding-side alignment mark (11b).
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Komuta does teach wirings that electrically connect the base-side alignment marks and the measurement terminals, and a wiring of the bonding-side semiconductor chip electrically connects the base-side alignment marks to each other.
Morita teaches, Fig. 17, [0010, 0063, 0084, 0090] & based on semiconductor devices, wirings (consider 251) that electrically connect the base-side alignment marks (consider portions of left & right 252) and the measurement terminals (consider 221), and a wiring (260) of the bonding-side semiconductor chip electrically connects the base-side alignment marks (230) to each other (Fig. 17).
As taught Morita, one of ordinary skill in the art would utilize & modify the above teaching to obtain wirings & a wiring of the bonding-side semiconductor chip electrically connects the base-side alignment marks to each other as claimed, because it aids in improving the connection stability & improving the device performance. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Morita in combination with Komuta due to above reason.
(*) The limitation “…configured to measure conduction” is merely a functional/intended use limitation that does not structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114. Additionally, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Re claim 6, Komuta teaches, under BRI, Figs. 6A & 9A, [0041-0042], a bonding-side semiconductor chip (10-1) comprising:
-a plurality of bonding-side alignment marks (11a); and
wherein, in a case in which the bonding-side semiconductor chip (10-1) is bonded to a base-side semiconductor chip (10-2) such that the bonding-side alignment marks (11a) overlap with a plurality of base-side alignment marks (11b) that are provided on the base-side semiconductor chip (10-2) and are electrically connected to measurement terminals (12, 13) (based on conductive materials) for measuring conduction (*).
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Komuta does not teach a wiring that electrically connects the bonding-side alignment marks to each other; and the wiring electrically connects the base-side alignment marks to each other, and wherein in a state in which the bonding-side semiconductor chip is so bonded, the wiring creates an electrical connection between the base-side alignment marks by virtue of the bonding-side alignment marks overlapping with the base-side alignment marks.
Morita teaches, Fig. 17, [0010, 0063, 0084, 0090] & based on semiconductor devices, a wiring (consider 260) that electrically connects the bonding-side alignment marks (consider left & right portions of 252) to each other; and the wiring (260) electrically connects the base-side alignment marks (230) to each other, and wherein in a state in which the bonding-side semiconductor chip is so bonded, the wiring (260) creates an electrical connection between the base-side alignment marks (230) by virtue of the bonding-side alignment marks (left & right portions of 252) overlapping with the base-side alignment marks (250).
As taught Morita, one of ordinary skill in the art would utilize & modify the above teaching to obtain wirings electrically connecting to the alignment marks, and wherein in a state in which the bonding-side semiconductor chip is so bonded, the wiring creates an electrical connection between the base-side alignment marks by virtue of the bonding-side alignment marks overlapping with the base-side alignment marks as claimed, because it aids in improving the connection stability & improving the device performance. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Morita in combination with Komuta due to above reason.
(*) The limitation “…for measuring conduction” is merely a functional/intended use limitation that does not structurally distinguish the claimed invention over the prior arts. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed.Cir.1997). Further, the prior art structure is capable of performing the functional/intended use, then it meets the claim. In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458,459 (CCPA 1963). See MPEP §2114. Additionally, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Response to Arguments
4. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
The claims amended with newly added features, interpretation & rejection under Komuta and Morita are changed to meet the currently amended claims. Details included in the above rejection.
Conclusion
5. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 4/1/26