DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Species I, as presented in at least Fig. 2A, in the reply filed on 29 December 2025 is acknowledged. The Restriction Requirement mailed 25 November 2025 is withdrawn in light of the prior art found, as said prior art reads on all species. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Regarding Claim s 2, 4, 5, & 13, th e s e claim s recite: “a/the connected structure ”. However, th is feature is not shown and/or is not designated by an associated reference character in any of the present figures. Regarding Claim 5, this claim recites: “ a first central axis of the connected structure ” ; “ a second central axis of the first bit line structure ” ; “ first central axis of the first extension portion ” . However, these features are not shown and/or are not designated by associated reference character s , respectively, in any of the present figures . Regarding Claim 6 , this claim recites: “ the plurality of extension portion pairs are spaced apart from each other by the first distance ”. However, th is feature is not shown and/or is not designated by an associated reference character in any of the present figures. Regarding Claim 13 , this claim recites: “ a first central axis of each the plurality of extension portions ”; “ a second central axis of the corresponding bit line structure ”. However, these features are not shown and/or are not designated by associated reference character s , respectively, in any of the present figures. Therefore, the above features must be shown and designated by associated reference characters or the features must be canceled from the claims. No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: DRAM DEVICE WITH EXTENDED BIT LINE STRUCTURES . The disclosure is objected to because of the following informalities: The disclosure does not provide reference characters for a number of claimed features. See objections in the Drawings section for details. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim s 2, 4 – 6, & 13 – 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding Claim 2, Lin. 2 recites the limitation “ a connected structure of the first extension portion and the first bit line structure ”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “ a connected structure , comprising the first extension portion and the first bit line structure ” Regarding Claims 4 & 5, These claims and are dependent upon C laim 2. Regarding Claim 5, Lin. 4 recites the limitation " the first central axis of the first extension portion ". However, t here is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as “ the first central axis of the connected structure ”. Regarding Claim 6, Lin. 2 recites the limitation “ the plurality of extension portion pairs are spaced apart from each other by the first distance ”. However, this limitation is unclear in light of the specification, in general, and the elected species, specifically. Based on Fig. 1A—also corresponding to the elected species in Fig. 2A— the plurality of extension portion pairs are spaced apart from each other by a distance greater than t he first distance . For the purposes of examination, this limitation will be interpreted as “ the plurality of extension portion pairs are spaced apart from each other by a distance greater than the first distance ” . Regarding Claim 13, Lin. 10 recites the limitation “ a connected structure of each of the plurality of extension portion s and a corresponding bit line structure of the plurality of bit line structures”. However, this language is ambiguous, rendering the claim indefinite. The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “ each connected structure of a plurality of connected structures comprises a pair of extension portion s of the plurality of extension portions and a corresponding bit line structure of the plurality of bit line structures ” Regarding Claims 1 4 – 17, These claims depend upon Claim 13. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim s 1 – 20 are rejected under 35 U.S.C. 102 as being anticipated by JEONG ( US 20130256769 A1 ). Regarding Claim 1, JEONG discloses: A semiconductor device (Fig. 1A & 1C; Par. 80) comprising: a substrate (Fig. 1C: 1; Par. 79) including a cell region (Fig. 1A: CAR less the ERs; Fig. 1C: CAR; hereinafter denoted CR) and an interface region (Fig. 1A: PCR and rightmost ER; Fig. 1C: PCR; hereinafter denoted IR); a gate electrode (Fig. 1A: WL; Par. 61) disposed within the cell region of the substrate and extending in a first horizontal direction (Fig. 1A: D2) that is parallel to an upper surface of the substrate; a plurality of bit line structure pairs (Annotated Fig. 1A: BLSP1 and BLSP2; Par. 81) crossing the gate electrode and extending in a second horizontal direction (Annotated Fig. 1A: D3) that is parallel to the upper surface of the substrate and intersects the first horizontal direction, each bit line structure pair including a first bit line structure (Annotated Fig. 1A: BLS1) and a second bit line structure (Annotated Fig. 1A: BLS2) that are spaced apart from each other in the first horizontal direction; and a plurality of extension portion pairs (Annotated Fig. 1A Cropped: EPP1 and EPP2) disposed within the interface region and spaced apart from each other in the first horizontal direction (As seen in Annotated Fig. 1A), each extension portion pair including a first extension portion (Annotated Fig. 1A Cropped: EP1) and a second extension portion (Annotated Fig. 1A Cropped: EP2) that are connected to the first bit line structure of a corresponding bit line structure pair and the second bit line structure thereof, respectively (As seen in Annotated Fig. 1A Cropped), wherein the plurality of bit line structure pairs are spaced apart from each other by a first distance (Annotated Fig. 1A Cropped: L1), wherein, in each bit line structure pair, the first bit line structure and the second bit line structure are spaced apart from each other by the first distance (As seen in Annotated Fig. 1A Cropped), wherein, in each extension portion pair, the first extension portion and the second extension portion are spaced apart from each other at a second distance (Annotated Fig. 1A Cropped: L2) less than the first distance, and wherein the first distance and the second distance are measured in the first horizontal direction. Regarding Claim 2, JEONG discloses: The semiconductor device of claim 1, wherein a connected structure, comprising the first extension portion and the first bit line structure, has a first horizontal width (Annotated Fig. 1A Cropped: W1) greater than a second horizontal width (Annotated Fig. 1A Cropped: W2) of the first bit line structure, and wherein the first horizontal width and the second horizontal width are measured in the first horizontal direction. Regarding Claim 3, JEONG discloses: The semiconductor device of claim 1, wherein the first extension portion protrudes in the first horizontal direction from one side of the first bit line structure (As seen in Annotated Fig. 1A Cropped). Regarding Claim 4, JEONG discloses: The semiconductor device of claim 2, wherein the connected structure is disposed in the interface region (As seen in Annotated Fig. 1A). Regarding Claim 5, JEONG discloses: The semiconductor device of claim 2, wherein a first central axis (Annotated Fig. 1A Cropped: CA1) of the connected structure is offset from a second central axis (Annotated Fig. 1A Cropped: CA2) of the first bit line structure in the first horizontal direction, and wherein the first central axis of the connected structure and the second central axis of the first bit line structure are parallel to the second horizontal direction. Regarding Claim 6, JEONG discloses: The semiconductor device of claim 1, wherein the plurality of extension portion pairs are spaced apart from each other by a distance greater than the first distance (Annotated Fig. 1A Cropped: L’). Regarding Claim 7, JEONG discloses: The semiconductor device of claim 1, wherein the first extension portion is materially continuous with the first bit line structure (As seen in Annotated Fig. 1A), and wherein the second extension portion is materially continuous with the second bit line structure (As seen in Annotated Fig. 1A). Regarding Claim 8, JEONG discloses: The semiconductor device of claim 7, wherein each of the first extension portion and the second extension portion includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked on the substrate. (Fig. 1C: BL—shown as a single conductive layer; Par. 68—may be construed to include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked on 1. Further, as the first and second extension portions are materially continuous with the first and second bit line structures—each represented by BL—respectively, the limitations of this claim are satisfied.) Regarding Claim 9, JEONG discloses: The semiconductor device of claim 1, further comprising: a first buried contact (Fig. 1A: the middle DDC; Par. 72) disposed in the interface region and disposed in a space between two adjacent extension portion pairs; and (Annotated Fig. 1A: the middle DDC is—partially—disposed in the in IR and disposed in the space between BLSP1 and BLSP2 and, thus, in the space between EPP1 and EPP2.) a second buried contact (Fig. 1C: BC—Par. 73—which is below 60—Par. 76—as seen in Fig. 1A) disposed in the interface region and disposed in a space between the first extension portion and the second extension portion in each extension portion pair, (Annotated Fig. 1A: 60—and thus BC—is disposed in IR and disposed in the space between BLS1 and BLS2 in both BLSP1 and BLSP2—and thus in the space between EP1 and EP2 in both EPP1 and EPP2.) wherein a first horizontal width (Fig. 1C: width of BC as seen in BB’ section, where BB’ is parallel to D2) of the second buried contact is narrower than a second horizontal width (Fig. 1C: width of DC as seen in BB’ section, where DC and DDC have the same shape; Par. 72) of the first buried contact, and wherein the first horizontal width and the second horizontal width are measured in the first horizontal direction. Regarding Claim 10, JEONG discloses: The semiconductor device of claim 9, wherein a lower end of the second buried contact is at a higher level than a lower end of the first buried contact (As seen in Fig. 1C). Regarding Claim 11, JEONG discloses: The semiconductor device of claim 9, further comprising: a third buried contact (Annotated Fig. 1A: BC disposed in CR and in the space between BLSP1 and BLSP2, where the location of said BC is indicated by an associated 60) disposed in the cell region and disposed in a space between two adjacent bit line structure pairs; and a fourth buried contact (Annotated Fig. 1A: BC disposed in CR and in the space between BLS1 and BLS2 in both BLSP1 and BLSP2, where the location of said BC is indicated by an associated 60) disposed in the cell region and disposed in a space between the first bit line structure and the second bit line structure in each bit line structure pair, wherein a third horizontal width of the third buried contact and a fourth horizontal width of the fourth buried contact have the same width (Fig. 1C: the horizontal width of all BCs are the same in the BB’ section, where BB’ runs parallel to D2), and wherein the third horizontal width and the fourth horizontal width are measured in the first horizontal direction. Regarding Claim 12, JEONG discloses: The semiconductor device of claim 1, further comprising: a first edge insulating structure (Fig. 1C: portion of 27—Par. 68—contacting BL associated with EP1 and BLS1) contacting the first extension portion and the first bit line structure; and a second edge insulating structure (Fig. 1C: portion of 27—Par. 68—contacting BL associated with EP2 and BLS2) contacting the second extension portion and the second bit line structure. Regarding Claim 13, JEONG discloses: A semiconductor device (Fig. 1A & 1C; Par. 80) comprising: a substrate (Fig. 1C: 1; Par. 79) including a cell region (Fig. 1A: CAR less the ERs; Fig. 1C: CAR; hereinafter denoted CR) and an interface region (Fig. 1A: PCR and rightmost ER; Fig. 1C: PCR; hereinafter denoted IR); a gate electrode (Fig. 1A: WL; Par. 61) disposed within the cell region of the substrate and extending in a first horizontal direction (Fig. 1A: D2) that is parallel to an upper surface of the substrate; a plurality of bit line structures (Annotated Fig. 1A: BLS1s and BLS2s; Par. 81) crossing the gate electrode and extending in a second horizontal direction (Annotated Fig. 1A: D3) intersecting the first horizontal direction, wherein the second horizontal direction is parallel to the upper surface of the substrate; and a plurality of extension portions (Annotated Fig. 1A Cropped: EP1s, EP2s, EP3s, and EP4s) disposed in the interface region (As seen in Annotated Fig. 1A) and connected to the plurality of bit line structures (As seen in Annotated Fig. 1A Cropped), respectively, wherein each connected structure of a plurality of connected structures comprises a pair of extension portions of the plurality of extension portions and a corresponding bit line structure of the plurality of bit line structures and has a first horizontal width (Annotated Fig. 1A Cropped: W3) greater than a second horizontal width (Annotated Fig. 1A Cropped: W2) of the corresponding bit line structure, wherein the first horizontal width and the second horizontal width are measured in the first horizontal direction (As seen in Annotated Fig. 1A Cropped), wherein a first central axis (Annotated Fig. 1A Cropped: CA3) of each the plurality of extension portions and a second central axis (Annotated Fig. 1A Cropped: CA2) of the corresponding bit line structure extend in the second horizontal direction, wherein the first central axis is aligned with the second central axis (Annotated Fig. 1A Cropped: CA1 and CA3 are both parallel to D3 and, thus, aligned with each other), wherein the plurality of bit line structures are spaced apart from each other by a first distance (Annotated Fig. 1A Cropped: L1), wherein the plurality of extension portions are spaced apart from each other by a second distance (Annotated Fig. 1A Cropped: L2) less than the first distance, and wherein the first distance and the second distance are measured in the first horizontal direction (As seen in Annotated Fig. 1A Cropped). Regarding Claim 14, JEONG discloses: The semiconductor device of claim 13, wherein each of the plurality of extension portions include a pair of extension portions which are connected to opposite side surfaces of a corresponding bit line structure of the plurality of bit line structures, respectively, (As seen in Annotated Fig. 1A Cropped) and wherein the corresponding bit line structure is disposed in a space between the pair of extension portions (As seen in Annotated Fig. 1A Cropped). Regarding Claim 15, JEONG discloses: The semiconductor device of claim 13, further comprising: a plurality of first buried contacts (Annotated Fig. 1A: DC; Par. 64), each of the plurality of first buried contacts disposed in a space between corresponding two adjacent bit line structures of the plurality of bit line structures in the cell region (As seen in Annotated Fig. 1A); and a plurality of second buried contacts (Fig. 1C: the BC—Par. 73—which are below 60—Par. 76—disposed in IR, as seen in Fig. 1A), each of the plurality of second buried contacts disposed in a space between corresponding two adjacent extension portions of the plurality of extension portions in the interface region, (Annotated Fig. 1A: each 60—and thus BC—in IR is disposed in a space between corresponding two adjacent extension portions of the plurality of extension portions.) wherein a first horizontal width (Fig. 1C: width of BC as seen in BB’ section, where BB’ is parallel to D2) of each of the plurality of second buried contacts is less than a second horizontal width (Fig. 1C: width of DC as seen in BB’ section) of each of the plurality of first buried contacts, and wherein the first horizontal width and the second horizontal width are measured in the first horizontal direction. Regarding Claim 16, JEONG discloses: The semiconductor device of claim 15, wherein lower ends of the plurality of second buried contacts are at a higher level than lower ends of the plurality of first buried contacts (As seen in Fig. 1C). Regarding Claim 17, JEONG discloses: The semiconductor device of claim 13, wherein each of the plurality of extension portions is materially continuous with a corresponding bit line structure of the plurality of bit line structures (As seen in Annotated Fig. 1A). Regarding Claim 18, JEONG discloses: A semiconductor device (Fig. 1A & 1C; Par. 80) comprising: a substrate (Fig. 1C: 1; Par. 79) including a cell region (Fig. 1A: CAR less the ERs; Fig. 1C: CAR; hereinafter denoted CR) and an interface region (Fig. 1A: PCR and rightmost ER; Fig. 1C: PCR; hereinafter denoted IR); a gate electrode (Fig. 1A: WL; Par. 61) disposed within the cell region of the substrate and extending in a first horizontal direction (Fig. 1A: D2) that is parallel to an upper surface of the substrate; a first bit line structure (Annotated Fig. 1A: BLS1—Par. 81—including the surrounding portions of 50, 47a, and 45—as seen in Fig. 1C—for the first bit line structure in CR) crossing the gate electrode and extending in a second horizontal direction (Annotated Fig. 1A: D3) that is parallel to the upper surface of the substrate and intersects the first horizontal direction; a second bit line structure (Annotated Fig. 1A: BLS2—Par. 81—including the surrounding portions of 50, 47a, and 45—as seen in Fig. 1C—for the second bit line structure in CR) crossing the gate electrode and extending in the second horizontal direction, wherein the second bit line structure is adjacent to the first bit line structure (As seen in Annotated Fig. 1A); a first buried contact (Fig. 1C: BC—Par. 73—which is below 60—Par. 76—as seen in Fig. 1A) disposed in a space between the first bit line structure and the second bit line structure (As seen in Annotated Fig. 1A); a landing pad (Fig. 1C: BEP; Par. 73) electrically connected to the first buried contact (Par. 73) and disposed on the first bit line structure (Fig. 1C: BEP is disposed on the portion of 50 surrounding BLS1—the leftmost BL in the BB’ region—which is part of the first bit line structure); a capacitor structure (Fig. 1C: CP; Par. 76) electrically connected to the landing pad and disposed on the landing pad (As seen in Fig. 1C); and a pair of inner extension portions (Annotated Fig. 1A Cropped: EP1 and EP2) disposed within the interface region (As seen in Annotated Fig. 1A) and connected to a first surface of the first bit line structure and a second surface of the second bit line structure, respectively, wherein the first surface is adjacent to the second surface (As seen in Annotated Fig. 1A Cropped), wherein the first bit line structure and the second bit line structure are spaced apart from each other by a first distance (Annotated Fig. 1A Cropped: L1), wherein the pair of inner extension portions are spaced apart from each other by a second distance (Annotated Fig. 1A Cropped: L2) less than the first distance, and wherein the first distance and the second distance are measured in the first horizontal direction. Regarding Claim 19, JEONG discloses: The semiconductor device of claim 18, further comprising: a pair of spacer structures (Fig. 1C: 51—Par. 76—and 27—Par. 68) disposed on opposite sides of the first bit line structure (Fig. 1C: 51 is on the topside and 27 is on the bottom side of the leftmost BL and its surrounding portions of 50, 47a, and 45 in the BB’ section, which is the first bit line structure.), wherein the first buried contact contacts one of the pair of spacer structures (Fig. 1C: BC contacts 27). Regarding Claim 20, JEONG discloses: The semiconductor device of claim 18, further comprising: a pair of outer extension portions (Annotated Fig. 1A Cropped: EP3 and EP4) disposed within the interface region (As seen in Annotated Fig. 1A) and connected to a third surface of the first bit line structure and a fourth surface of the second bit line structure, respectively, wherein the third surface of the first bit line structure is opposite to the first surface thereof, and wherein the fourth surface of the second bit line structure is opposite to the second surface thereof (As seen in Annotated Fig. 1A Cropped). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT Kenneth S. Stephenson whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-6686 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday through Friday, 9 A.M. to 5 P.M. (EST). . Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview — preferably at 4 P.M. (EST) — applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Julio Maldonado can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1864 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.S.S./ Examiner, Art Unit 2898 /JULIO J MALDONADO/ Supervisory Patent Examiner, Art Unit 2898