DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 3/3/2026 has been entered and thus claims 1-22 are currently pending in this application. The amendment to claims 11 and 22 overcomes the previous 112(b) rejection, therefore the 112(b) rejections are hereby withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Selvanayagam et al. 2024/0095568 of record in view of Chang et al. US PGPub. 2020/0028064. Regarding claim 1, Selvanayagam teaches an integrated circuit device (202, fig. 2C) [0069] comprising: a substrate (220, fig. 2C) [0073]; a Josephson junction (210, fig. 2C) [0073] on the substrate (220); external electrodes (206A, B, fig. 2C) [0075] on the substrate (220) and spaced apart from the Josephson junction (210); and bridge connections (214A, B, fig. 2C) [0080] connecting the Josephson junction (210) to the external electrodes (206A, B); wherein the Josephson junction (210) comprises a first layer (212A, fig. 2C) [0076] and a second layer (212B, fig, 2c) [0076]; a (middle) portion of a first bridge connection (214A, fig. 2C) of the bridge connections (214A, B) is above the substrate (220) between the first layer (212A) of the Josephson junction (210) and a first external electrode (206A, fig. 2C) of the external electrodes (206, B); and a (middle) portion of a second bridge connection (214B, fig. 2C) of the bridge connections (214A, B) is above the substrate (220) between the second layer (212B) of the Josephson junction (210) and a second external electrode (206B, fig. 2C) of the external electrodes (206A, B)(Selvanayagam et al., fig. 2C). But Selvanayagam does not teach wherein a (middle) portion of a first bridge connection (214A) of the bridge connections is suspended above and separated from the substrate (220) between the first layer (212A) of the Josephson junction (210) and a first external electrode (206A) of the external electrodes; and a (middle) portion of a second bridge connection (214B) of the bridge connections is suspended above and separated from the substrate (220) between the second layer (212B) of the Josephson junction (210) and a second external electrode (206B) of the external electrodes. However, Chang teaches an integrated circuit device (fig.3B) wherein a (middle) portion of a first bridge connection (320, fig. 3B) [0052] of the bridge connections (320) is suspended above (air gap 350, fig. 3B) [0052] and separated from the substrate (5, fig. 3B) [0035] between the first layer (11B, fig. 3B) [0047] of the Josephson junction (300, fig. 3B) [0047], [0052] and a first external electrode (11A, fig. 3B) [0042] of the external electrodes (11A) (Chang et al., fig. 3B). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the first and second bridge connections of Selvanayagam by adding the air gap as taught by Chang such that a (middle) portion of the first and second bridge connections of the bridge connections are suspended above (by the air gap) and separated (by the air gap) from the substrate between the first and second layers of the Josephson junction and a first and second external electrode because such structure is well known in the art and such structure is art recognized and suitable for the intended purpose of preventing lossy (energy absorption via two-level systems Chang et al., [0048] thereby increasing coherence times by eliminating lossy materials Chang et al., [0004]) (see MPEP 2144.07).
Regarding claim 5, Selvanayagam in view of Chang teaches the integrated circuit device of claim 1, wherein the Josephson junction (210) was formed by shadow evaporation [0077] (Selvanayagam et al., [0077]).
Regarding claim 7, Selvanayagam in view of Chang teaches the integrated circuit device of claim 1, wherein the Josephson junction is an Al/AlOx/Al junction (Selvanayagam et al., fig. 2C, [0076] and [0087]).
Regarding claim 8, Selvanayagam in view of Chang teaches the integrated circuit device of claim 1, wherein the Josephson junction (210) is spaced apart from the external electrodes (206A, B) such that no part of the Josephson junction (210) is in direct contact with the external electrodes (206A, B) (Selvanayagam et al., fig. 2C).
Regarding claim 9, Selvanayagam in view of Chang teaches the integrated circuit device of claim 1, wherein: the Josephson junction (210) comprises a first layer (212A, fig. 2C) [0075] and a second layer (212B, fig. 2C) [0075]; a first bridge connection (214A, fig. 2C) [0080] is in direct contact with the first layer (212A) of the Josephson junction (210) and a first external electrode (206A) only; and a second bridge connection (214B, fig. 2C) [0080] is in direct contact with the second layer (212B) of the Josephson junction (210) and second external electrode (206B) only (Selvanayagam et al., fig. 2C).
Regarding claim 10, Selvanayagam in view of Chang teaches the integrated circuit device of claim 9, wherein the first layer (212A) and the second layer (212B) of the Josephson junction (210) comprise aluminium [0076] and wherein a barrier layer (216, fig. 2C) [0075] disposed between the first layer (212A) and the second layer (212B) comprises aluminium oxide [0087] (Selvanayagam et al., fig. 2C, [0076] and [0087]).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Selvanayagam et al. 2024/0095568 of record in view of Chang et al. US PGPub. 2020/0028064 as applied to claim 1 above, and further in view of McDermott et al. US PGPub. 2025/0331430 of record. Regarding claim 2, Selvanayagam in view of Chang does not teach the integrated circuit device of claim 1, wherein the Josephson junction (210) is a component of a superconducting qubit. However, McDermott teaches an integrated circuit (fig. 1) [0010], [0025] including a Josephson junction (fig. 1), wherein the Josephson junction (fig. 1) is a component of a superconducting qubit [0026] (McDermott et al., fig. 1, [0026]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to substitute the Josephson junction of Selvanayagam with the superconducting qubit Josephson junction of McDermott because superconducting qubits are well known in the art and such material/structure are art recognized and suitable for the intended purpose of providing qubit arrays with suppressed correlated errors (McDermott et al., [0004]) (see MPEP 2144.07).
Regarding claim 3, Selvanayagam in view of Chang and McDermott teaches the integrated circuit device of claim 2, wherein the superconducting qubit (fig. 1) is a transmon qubit [0026], gmon qubit, or a fluxmon qubit (McDermott et al., fig. 1, [0026]).
Regarding claim 4, Selvanayagam in view of Chang and McDermott teaches the integrated circuit device of claim 2, wherein the integrated circuit device (fig. 1) is a quantum processing unit (McDermott et al., fig. 1, [0020]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Selvanayagam et al. 2024/0095568 of record in view of Chang et al. US PGPub. 2020/0028064 as applied to claim 5 above, and further in view of Sato et al. US PGPub. 2024/0099160 of record. Regarding claim 6, Selvanayagam in view of Chang does not teach the integrated circuit device of claim 5, wherein the Josephson junction (210) is a cross type Josephson junction. However, Sato teaches a Josephson junction (200, fig. 12)[0113] is a cross type Josephson junction (fig. 12) (Sato et al, fig. 12) At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to substitute the Josephson junction of Selvanayagam with the cross type Josephson junction of Sato because cross type Josephson junction are well known in the art and such material/structure are art recognized and suitable for the intended purpose of providing a quantum device that can suppress decoherence (Sato et al., [0130]) (see MPEP 2144.07).
Response to Arguments
Applicant’s arguments with respect to claims 1-10 been considered but are moot because the new ground of rejection does not rely on the same combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 11-22 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a method of manufacturing an integrated circuit device comprising “depositing a resist over the substrate, the Josephson junction and the external electrodes; patterning the resist such that contact pads on the Josephson junction and the external electrodes are exposed, and such that the patterned resist between the contact pads defines bridge connection support portions” in combination with “forming bridge connections by removing the resist and the superconducting thin film except for the superconducting thin film deposited on the contact pads and over the bridge connection support portions” as recited in claim 11; and an integrated circuit device produced by “depositing a resist over the substrate, the Josephson junction and the external electrodes; patterning the resist such that contact pads on the Josephson junction and the external electrodes are exposed, and such that the patterned resist between the contact pads defines bridge connection support portions” in combination with “forming bridge connections by removing the resist and the superconducting thin film except for the superconducting thin film deposited on the contact pads and over the bridge connection support portions” as recited in claim 22.
Claims 12-21 are also allowed for further limiting and depending upon allowed claim 11. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892