CTFR 18/371,889 CTFR 101466 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1, 3-4, 11, and 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Galatage et al. (US Patent Pub 20230402507 A1) in view of Cheng et al. (US Patent Pub 20230111270 A1) . Regarding Claim 1, Galatage teaches a semiconductor structure comprising: a second field effect transistor (FET) stacked above a first FET (Fig. 1C, second FET 101 stacked above first FET 140); a horizontal inner spacer located in a spacer region of the first FET (Fig. 1C, horizontal inner spacer 120); An inner spacer located in a spacer region (Fig. 1C, inner spacer 132) and a middle dielectric isolation layer separating the first FET from the second FET (Fig. 1C, middle dielectric isolation layer 150. The middle dielectric separates the inner spacer of the upper FET from the horizontal inner spacer of the lower FET). Galatage fails to the inner spacer is fork shaped, wherein the fork shaped inner spacer has a bottommost surface in direct physical contact with a topmost surface of the middle dielectric isolation layer. However, Cheng teaches a semiconductor structure FET semiconductor structure with a fork shaped inner spacer wherein the fork shaped inner spacer has a bottommost surface in direct physical contact with a topmost surface of the middle dielectric isolation layer (Cheng, Fig. 20 teaches fork shaped inner spacer 254 in contact with the topmost surface of the middle dielectric isolation layer 2080B/264). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teaching of Cheng into the method of Galatage by forming the semiconductor structure having a fork shaped inner spacer located in a spacer region of the second (upper) FET, and a middle dielectric isolation layer separating the first FET from the second FET and separating the horizontal inner spacer from the fork shaped inner spacer, wherein the fork shaped inner spacer has a bottommost surface in direct physical contact with a topmost surface of the middle dielectric isolation layer. The ordinary artisan would have been motivated to modify Galatage in the manner set forth above for at least the purpose of reducing bulk leakage while isolating channel members from the substrate (Cheng, paragraph 0013). Regarding Claim 3, Galatage in view of Cheng teaches the semiconductor structure of Claim 1, further comprising a dielectric pillar located laterally adjacent to the fork shaped inner spacer and located on the topmost surface of the middle dielectric isolation layer (Galatage, fig. 1C, dielectric pillar 102 located on the topmost surface of 150). Regarding Claim 4, Galatage in view of Cheng teaches the semiconductor structure of Claim 3, wherein the first FET and the second FET comprise a common gate structure, and wherein the dielectric pillar is located laterally adjacent to a gate extension of the second FET (Galatage, Fig. 1C, common gate structures 122/172. Dielectric pillar 102 laterally adjacent to gate extension 125 of the second FET). Regarding Claim 11, Galatage in view of Cheng teaches the semiconductor structure of Claim 1, wherein the first FET comprises first source/drain regions, and the second FET comprises second source/drain regions (Galatage, Fig. 1C, First FET 140 comprising first source drain regions 105c/105d, and second FET 101 comprising second source/drain regions 105a/105b). Regarding Claim 14, Galatage in view of Cheng teaches the semiconductor structure of Claim 11, wherein the second source/drain regions are diamond shaped (The applicant’s own specification (paragraph 0096) defines “diamond shaped” as having faceted sidewalls (also shown in fig. 18D element 50). Cheng, Fig. 27 teaches second source/drain 256 with faceted sidewalls). Regarding Claim 15, Galatage in view of Cheng teaches the semiconductor structure of Claim 11, wherein the second source/drain regions are non-diamond shaped (Galatage, Fig. 1C shows second source/drain regions 105a/105b are non-diamond shaped). Regarding Claim 16, Galatage in view of Cheng teaches the semiconductor structure of Claim 11, further comprising a first source/drain contact structure contacting one of the first source/drain regions, and a second source/drain contact structure contacting one of the second source/drain regions (Galatage, Fig. 1C, first source/drain contact structures 118c/118d contacting the first source/drain regions 105c/105d, and second source/drain contact structures 118a/118b contacting the second source/drain regions 105a/105b). Regarding Claim 17, Galatage in view of Cheng teaches the semiconductor structure of Claim 4, further comprising a gate contact structure contacting a gate electrode of the common gate structure (Galatage, Fig. 1C, gate contact structure 175a contacting gate electrode 177). Regarding Claim 18, Galatage in view of Cheng teaches the semiconductor structure of Claim 1, wherein the horizontal inner spacer and the fork shaped inner spacer are composed of a compositionally same inner dielectric spacer material (Galatage, paragraph 0063 teaches the horizontal inner spacer may be formed of an oxide such as a silicon oxide. Cheng, paragraph 0030 teaches the fork shaped inner spacer 254 can be silicon oxide) . 07-22-aia AIA Claim (s) 5-6, 10, 12-13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Galatage in view of Cheng as applied to claim s 1, 3-4, 11, and 14-18 above, and further in view of Reznicek et al. (US 11,315,938 B1) . Regarding Claim 5, Galatage in view of Cheng teaches the semiconductor structure of Claim 3. Galatage in view of Cheng fails to teach the semiconductor structure wherein the first FET is a first nanosheet FET comprising a plurality of vertically stacked and spaced apart first semiconductor channel material nanosheets, and the second FET is a second nanosheet FET comprising a plurality of vertically stacked and spaced apart second semiconductor channel material nanosheets. However, Reznicek teaches a stacked FET semiconductor structure wherein the first FET is a first nanosheet FET comprising a plurality of vertically stacked and spaced apart first semiconductor channel material nanosheets, and the second FET is a second nanosheet FET comprising a plurality of vertically stacked and spaced apart second semiconductor channel material nanosheets (Reznicek et al., fig. 18, first FET 22 contains stacked channel material, second FET 24 contains stacked channel material, column 7 lines 36-54 teaches the channel materials are nanosheets). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teaching of Reznicek into the method of Galatage in view of Cheng by forming the semiconductor structure wherein the first FET is a first nanosheet FET comprising a plurality of vertically stacked and spaced apart first semiconductor channel material nanosheets, and the second FET is a second nanosheet FET comprising a plurality of vertically stacked and spaced apart second semiconductor channel material nanosheets. The ordinary artisan would have been motivated to modify Galatage in view of Cheng in the manner set forth above for at least the purpose of increasing the density of semiconductors (Reznicek, , Column 4 lines 40-44). Regarding Claim 6, Galatage in view of Cheng and Reznicek teaches the semiconductor structure of Claim 5, wherein each first semiconductor channel material nanosheet of the plurality of vertically stacked and spaced apart first semiconductor channel material nanosheets is composed of a semiconductor material that is compositionally the same as a semiconductor material that provides each second semiconductor channel material nanosheet of the plurality of vertically stacked and spaced apart second semiconductor channel material nanosheets (Reznicek et al., column 6 lines 60-67, column 7 lines 1-3). Regarding Claim 10, Galatage in view of Cheng teaches the semiconductor structure of Claim 3, but fails to specifically teach the semiconductor structure further comprising a gate cut dielectric pillar located adjacent to the first FET and the second FET, wherein the gate cut dielectric pillar lands on a surface of a shallow trench isolation structure. However, Reznicek teaches a stacked FET semiconductor structure comprising a gate cut dielectric pillar located adjacent to the first FET and the second FET, wherein the gate cut dielectric pillar lands on a surface of a shallow trench isolation structure (Reznicek, fig. 19, gate cut dielectric pillar 56). It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teaching of Reznicek into the method of Galatage in view of Cheng by forming the semiconductor structure further comprising a gate cut dielectric pillar located adjacent to the first FET and the second FET, wherein the gate cut dielectric pillar lands on a surface of a shallow trench isolation structure. The ordinary artisan would have been motivated to modify Galatage in view of Cheng in the manner set forth above for at least the purpose of isolating adjacent FET structures (Reznicek, , Column 10 lines 8-10). Regarding Claim 12, Galatage in view of Cheng and Reznicek teaches the semiconductor structure of Claim 11, wherein the first source/drain regions are spaced apart from the second source/drain regions by an interlayer dielectric (ILD) layer (Reznicek, fig. 20B, interlayer dielectric (ILD) layer 164 separates source/drain regions 160 and 162). Regarding Claim 13, Galatage in view of Cheng and Reznicek teaches the semiconductor structure of Claim 12, wherein at least the first source/drain regions and the ILD layer are confined in an area between a pair of gate dielectric spacers (Reznicek et al., fig. 20b, 160 and 164 are between gate dielectric spacers 166 of adjacent transistors). Regarding Claim 20, Galatage in view of Cheng and Reznicek teaches the semiconductor structure of Claim 1, wherein the first FET is of a first conductivity type and the second FET is a second conductivity type, wherein the first conductivity type is the same as the second conductivity type (Reznicek et al., column 4 lines 50-57 teaches the first and second FETS are both n-type or p-type) . 07-22-aia AIA Claim (s) 7-8 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Galatage in view of Cheng and Reznicek as applied to claim s 5-6, 10, 12-13, and 20 above, and further in view of Smith et al. (Us Patent Pub 20190172755 A1) . Regarding claim 7, Galatage in view of Cheng and Reznicek teaches a semiconductor structure with a second set of channel material nanosheets stacked over a first set of channel material nanosheets, but fails to teach that the first set is compositionally different from the second set. However, Smith teaches a plurality of vertically stacked and spaced apart first and second semiconductor channel material nanosheets composed of a semiconductor material that are compositionally different (Smith, fig. 2D, 110 and 130, SiGe is compositionally different than Si). It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Smith into the method of Reznicek et al. in view of Cheng et al. by fabricating the first and second semiconductor channel material nanosheets using semiconductor materials that are compositionally different. The ordinary artisan would have been motivated to modify Reznicek et al. in view of Cheng et al. in the manner set forth above for at least the purpose of removing the need to cover or block one active channel type area because the etch resistivities themselves will protect complementary and bulk materials from being etched (Smith, paragraph 0036). Regarding Claim 8, Galatage in view of Cheng, Reznicek and Smith teaches the semiconductor structure of Claim 5, wherein each first semiconductor channel material nanosheet of the plurality of vertically stacked and spaced apart first semiconductor channel material nanosheets has a first width, and each second semiconductor channel material nanosheet of the plurality of vertically stacked and spaced apart second semiconductor channel material nanosheets has a second width, wherein the first width is greater than the second width (Smith, fig. 2D, 130 has a greater width than 110). Regarding Claim 19, Galatage in view of Cheng, Reznicek and Smith teaches the semiconductor structure of Claim 1, wherein the first FET is of a first conductivity type and the second FET is a second conductivity type, wherein the first conductivity type is different from the second conductivity type (Smith, paragraph 0036 teaches the stacked transistors are a different conductivity type) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim(s) 1 and 3-20 have been considered but are moot in view of the new grounds of rejection as applied above. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICENTE R GONZALES whose telephone number is (571)272-3365. The examiner can normally be reached Monday - Friday 7:30 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /V.R.G./Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/371,889 Page 2 Art Unit: 2899 Application/Control Number: 18/371,889 Page 3 Art Unit: 2899 Application/Control Number: 18/371,889 Page 4 Art Unit: 2899 Application/Control Number: 18/371,889 Page 5 Art Unit: 2899 Application/Control Number: 18/371,889 Page 6 Art Unit: 2899 Application/Control Number: 18/371,889 Page 7 Art Unit: 2899 Application/Control Number: 18/371,889 Page 8 Art Unit: 2899 Application/Control Number: 18/371,889 Page 9 Art Unit: 2899
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