Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, and 9-14 is rejected under 35 U.S.C. 103 as being unpatentable over Takeya et al. (US-20220384406-A1 referred as Takeya) in view of Kim (US-20080278070-A1).
Regarding claim 1. Takeya discloses a display device, comprising:
a lower substrate which is stretchable ([0021, 0064], figure 1, a lower substrate #114 which is stretchable as mentioned in [0032], in this rejection figure 1 will be flipped 180 degrees to read on the claim language);
a plurality of pixels disposed on the lower substrate ([0063-0064], figure 1, a plurality of pixels #112a-112c disposed on a lower substrate #114);
a plurality of lower connection lines disposed on the lower substrate and connected to each of the plurality of pixels ([0063-0064], figure 1, a plurality of lower connection lines #116 disposed on the lower substrate #114 and connected to each of the plurality of pixels #112a-112c);
an upper substrate which is stretchable, and disposed opposite to the lower substrate ([0063-0064], figure 1, an upper substrate #132 which is stretchable, as mentioned in [0032], and also at the opposite side of the lower substrate #114);
a plurality of conductive patterns disposed below the upper substrate and connected to the plurality of pixels, respectively ([0063-0064], figure 1, a plurality of conductive patterns #122 disposed below the upper substrate #132 and connected to the plurality of pixels #112a-112c, respectively); and
a plurality of upper connection lines disposed below the upper substrate and connected to the plurality of conductive patterns ([0063-0064], figure 1, a plurality of upper connection lines #152 and connected to the plurality of conductive patterns #122).
wherein the plurality of conductive patterns is disposed on a vertical light emitting diode ([0067], figure 1, the plurality of conductive patterns #122 is seen disposed on a vertical light emitting diode #25 (since it is the specific element that emits light)).
Takeya lacks wherein a plurality of lower plate patterns is disposed between the lower substrate and the plurality of pixels; and
wherein a plurality of upper plate patterns is disposed between the upper substrate and the plurality of conductive patterns, and
wherein each of the plurality of upper plate patterns overlaps at least a portion of each of the plurality of lower plate patterns.
Kim discloses wherein a plurality of lower plate patterns is disposed between the lower substrate and the plurality of pixels ([0043], figure 2, a plurality of lower plate patterns #103 and #104 are disposed in between the lower substrate #101 and the plurality of pixels #106/107/108. In the figure 2 there is one pixel across the plurality of pixels seen in figure 1); and
wherein a plurality of upper plate patterns is disposed between the upper substrate and the plurality of conductive patterns ([0043], figure 2, a plurality of upper plate patterns #153 are disposed in between the upper substrate and the plurality of conductive patterns #151. The single conductive pattern #151 of figure 2 is seen from the plurality of conductive patterns in figure 1 needed), and
wherein each of the plurality of upper plate patterns overlaps at least a portion of each of the plurality of lower plate patterns ([0043], figure 2, each of the plurality of upper plate patterns #153 overlaps a portion of each of the plurality of lower plate patterns #103/104).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Takeya to include the lower plate patterns and the upper plate patterns as taught by Kim in order to increase device versatility, reduce device failure, and to increase the circuits lifetime.
Regarding claim 4. Takeya as modified discloses wherein each of the plurality of pixels includes a vertical light emitting diode electrically connected to one of the plurality of conductive patterns ([0068], figure 1, each of the plurality of pixels #112a-112c consist of vertical light emitting diodes #112 which is connected to each of the plurality of conductive patterns #122).
Regarding claim 5. Takeya as modified discloses wherein the plurality of conductive patterns are configured to have only a first driving voltage applied. ([0072], the plurality of conductive patterns #122 is conductive, therefore, they are ‘configured to’ have a voltage applied to them, thus reading on a first driving voltage).
Regarding claim 6. Takeya as modified discloses wherein the plurality of upper connection lines are configured to have only a first driving voltage applied. ([0080], figure 1, the plurality of upper connection lines #152 is conductive, therefore, they are ‘configured to’ have a voltage applied to them, thus reading on a first driving voltage).
Regarding claim 7. Takeya as modified discloses wherein the plurality of upper connection lines extends only in a first direction ([0080], figure 1, the plurality of upper connection lines #152 extends only in a (vertical) first direction).
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Regarding claim 9. Takeya as modified discloses wherein each of the plurality of conductive patterns includes a plurality of first conductive patterns, a plurality of second conductive patterns, a plurality of third conductive patterns, and a plurality of fourth conductive patterns disposed on a same layer ([0063], figure 1 annotated above, the plurality of conductive patterns #122 consists of a plurality of for the first conductive patterns #122a, second conductive patterns #122b, third conductive patterns #122c, and fourth conductive patterns #122d all disposed on a same layer. The plurality of each conductive patterns stems from the plurality required to circuit the entire grid seen in figure 2).
Regarding claim 10. Takeya as modified discloses wherein each of the plurality of fourth conductive patterns is configured to have only a first driving voltage applied, and
each of the a plurality of first conductive patterns, a plurality of second conductive patterns, and a plurality of third conductive patterns is configured to have a gate voltage or a second driving voltage applied ([0063], figure 1 annotated above, the fourth conductive pattern #122d is conductive, therefore they are ‘configured to’ have a voltage applied to it, thus reading on a first driving voltage. The first, second, and third conductive pattern (#122a, #122b, #122c, respectively) are conductive, therefore they are ‘configured to’ having a voltage applied to them, thus reading on having a gate voltage/second driving voltage).
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Regarding claim 11. Takeya as modified discloses wherein in each of the plurality of pixels, a plurality of first pads, a plurality of second pads, and a plurality of third pads are formed,
each of the plurality of first conductive patterns is electrically connected to a corresponding one of the plurality of first pads through a first contact hole,
each of the plurality of the second conductive patterns is electrically connected to a corresponding one of the plurality of second pads through a second contact hole,
each of the plurality of the third conductive patterns is electrically connected to a corresponding one of the plurality of third pads through a third contact hole, and
each of the plurality of the fourth conductive pattern is electrically connected to a corresponding one of the plurality of light emitting diodes ([0080], figure 1 annotated above, in each plurality of pixels #112a-112c, a plurality of first pad #134a, plurality of second pad #134b, and a plurality of third pad #134c is formed (the plurality comes from the multiple required for the grid seen in figure 2). The first conductive pattern #122a is connected to the first pad #134a through a first contact hole which #152 fills in and allows conductivity through. please note the contact hole is made to the element #150 in which #152 fills in for (please note the plurality of figure 2). The second conductive pattern #122b is connected to the second pad #134b through a second contact hole which #152 fills in and allows conductivity through (please note the plurality of figure 2). The third conductive pattern #122c is connected to the third pad #134c through a third contact hole which #152 fills in and allows conductivity through (please note the plurality of figure 2). The fourth conductive pattern #122d is directly connected to the vertical light emitting diode #112a (please note the plurality of figure 2)).
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Regarding claim 12. Takeya as modified discloses wherein each of the plurality of upper connection lines includes a first upper connection line, a second upper connection line, a third upper connection line, and a fourth upper connection line, the first upper connection line connects the first conductive patterns, the second upper connection line connects the second conductive patterns, the third upper connection line connects the third conductive patterns, and the fourth upper connection line connects the fourth conductive patterns ([0080], figure 1 annotated above, the plurality of upper connection lines #152 consists of a first upper connection line #152a, a second upper connection line #152b, a third upper connection line #152c, and a fourth upper connection line #152d. The first upper connection line #152a is connected to the first conductive pattern #122a, the second upper connection line #152b is connected to the second conductive pattern #122b, the third upper connection line #152c is connected to the third conductive pattern #122c, and the fourth upper connection line #152d is connected to the fourth conductive pattern #122d).
Regarding claim 13. Takeya as modified discloses wherein the first upper connection line, the second upper connection line, the third upper connection line, and the fourth upper connection line extend only in a first direction (figure 1 annotated above, the first upper connection line #152a, a second upper connection line #152b, a third upper connection line #152c, and the fourth upper connection line #152d extend only in a first direction (vertical)).
Regarding claim 14. Takeya as modified discloses wherein the plurality of lower connection lines extends only in a second direction different from the first direction (figure 1, the plurality of lower connection lines #116 extend only in a second direction (horizontal)), and each of the plurality of lower connection lines is configured to have data voltage applied ([0072], figure 1, the plurality of lower connection lines #116 is conductive, therefore they are ‘configured to’ have a voltage applied to it, thus reading on a data voltage).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Takeya et al. (US-20220384406-A1 referred as Takeya) and Kim (US-20080278070-A1) in further view of Lee et al. (US-20220102422-A1 referred as Lee).
Regarding claim 2. Takeya as modified lacks wherein a plurality of lower line patterns is disposed between the lower substrate and the plurality of lower connection lines, and
a modulus of elasticity of each of the plurality of lower plate patterns and the plurality of lower line patterns is higher than a modulus of elasticity of the lower substrate.
Lee discloses wherein a plurality of lower line patterns is disposed between the lower substrate and the plurality of lower connection lines ([0199], figure 9, a plurality of lower line patterns #ELT2/ELT3 is disposed in between the lower substrate #BSL and the lower connection lines #TCL), and
a modulus of elasticity of each of the plurality of lower plate patterns and the plurality of lower line patterns is higher than a modulus of elasticity of the lower substrate ([0235], [0099], figure 9, the modulus elasticity of the lower plate patterns #ELT1 and the lower line patterns #ELT2 containing ITO (Indium Tin Oxide) is 113 GPa (see attached ‘Data Analysis’ of non patent literature to Carter et al.). The modulus elasticity of the stretchable lower substrate #BSL (which shares the same material as #UPL) containing fiber glass reinforced plastic is 95 GPa (see attached ‘conclusions’ of non patent literature to Li et al.). The modulus elasticity of the lower plate pattern #ELT1 and lower line patterns #ELT2 is higher than the modulus elasticity of lower substrate #BSL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Takeya as modified to include a modulus of elasticity of the lower plate patterns and the lower line patterns being higher than a modulus of elasticity of the lower substrate as taught by Lee in order to increase device versatility, reduce device failure, and to increase the circuits lifetime.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Takeya et al. (US-20220384406-A1 referred as Takeya) and Kim (US-20080278070-A1) in further view of Cho et al. (US-20210036060-A1 referred as Cho).
Regarding claim 3. Takeya as modified lacks wherein a plurality of upper line patterns is disposed between the upper substrate and the plurality of upper connection lines, and
a modulus of elasticity of each of the plurality of upper plate patterns and the plurality of upper line patterns is higher than a modulus of elasticity of the upper substrate.
Cho discloses wherein a plurality of upper line patterns is disposed between the upper substrate and the plurality of upper connection lines ([0162], figure 11, a plurality of upper line patterns #311 is disposed in between the upper substrate #560 and the plurality of upper connection lines #S3), and
a modulus of elasticity of each of the plurality of upper plate patterns and the plurality of upper line patterns is higher than a modulus of elasticity of the upper substrate ([0154], [0160], [0229], the modulus elasticity of the upper plate pattern #312 and the upper line pattern #311 containing ITO (Indium Tin Oxide) is 113 GPa (see attached ‘Data Analysis’ of non patent literature to Carter et al.). The modulus elasticity of the stretchable upper substrate #560 containing fiber glass reinforced plastic is 95 GPa (see attached ‘conclusions’ of non patent literature to Li et al.). The modulus elasticity of the upper plate pattern #312 and the upper line pattern #311 is higher than the modulus elasticity of upper substrate #560).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Takeya as modified to include upper plate patterns and upper line patterns with a modulus of elasticity of the upper plate patterns and the upper line patterns being higher than a modulus of elasticity of the upper substrate as taught by Cho in order to increase device versatility, reduce device failure, and to increase the circuits lifetime.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Takeya et al. (US-20220384406-A1 referred as Takeya) and Kim (US-20080278070-A1) in further view of Lee et al. (US-20220393084-A1 referred as Lee #2).
Regarding claim 8. Takeya as modified lacks wherein the plurality of lower connection lines includes a plurality of first lower connection lines extending in a first direction,
a plurality of second lower connection lines extending in a second direction different from the first direction, and
wherein the plurality of first lower connection lines are configured to have a gate voltage and a second driving voltage applied, and the plurality of second lower connection lines are configured to have a data voltage applied.
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Lee #2 discloses wherein the plurality of lower connection lines includes a plurality of first lower connection lines extending in a first direction ([0095], figure 10 annotated above, the plurality of lower connection lines #21 includes a first lower connection lines #21a which extends in the first direction (vertical)),
a plurality of second lower connection lines extending in a second direction different from the first direction ([0095], figure 10 annotated above, the plurality of lower connection lines #21 includes a second lower connection line #21b which extends in the second direction (horizontal)), and
wherein the plurality of first lower connection lines are configured to have a gate voltage and a second driving voltage applied, and the plurality of second lower connection lines are configured to have a data voltage applied ([0140], figure 10, the plurality of first lower connections #21a are conductive, therefore, they are 'configured to' have two different voltages be applied to them, thus reading on a gate voltage and a second driving voltage. The plurality of second lower connection lines #21b is also conductive, therefore they are ‘configured to’ have a data voltage applied to them, thus reading on a data voltage).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Takeya as modified to include parts of the plurality of lower connection lines extending in a first direction and the second direction as taught by Lee #2 in order to distribute weight across the device, increase device performance, and to enhance the versatility of uses for the device.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Takeya et al. (US-20220384406-A1 referred as Takeya) and Kim (US-20080278070-A1) in further view of Im et al. (US-20220375990-A1 referred as Im).
Regarding claim 15. Takeya as modified discloses wherein each of the plurality of conductive patterns includes a plurality of first lower conductive patterns, a plurality of second lower conductive patterns, a plurality of third lower conductive patterns, and a plurality of fourth lower conductive patterns disposed on a first layer ([0063], figure 1 annotated above, the plurality of conductive patterns #122 consists of a first lower conductive pattern #122a, a second lower conductive pattern #122b, a third lower conductive pattern #122c, and a fourth lower conductive pattern #122d all disposed on a same layer).
Takeya as modified lacks wherein a plurality of first upper conductive patterns and a plurality of second upper conductive patterns disposed on a second layer, each of the plurality of first lower conductive patterns is electrically connected to a corresponding one of the plurality of second upper conductive patterns, and a second lower conductive pattern of the plurality of second lower conductive patterns is electrically connected to a corresponding one of the plurality of second upper conductive patterns.
Im discloses wherein a plurality of first upper conductive patterns and a plurality of second upper conductive patterns disposed on a second layer, each of the plurality of first lower conductive patterns is electrically connected to a corresponding one of the plurality of second upper conductive patterns, and a second lower conductive pattern of the plurality of second lower conductive patterns is electrically connected to a corresponding one of the plurality of second upper conductive patterns ([0155], figure 8a, each figure in 8a is seen part of a larger grid seen in figure 5 to its own respective plurality of an element. The plurality of all elements of first upper conductive pattern #CNE1 and the second upper conductive pattern #CNE2 is disposed on a second layer of #INS1. The first lower conductive pattern #ELT1 is connected to the first upper conductive pattern #CNE1 and the second lower conductive pattern #ELT2 is connected to the second upper conductive pattern #CNE2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Takeya as modified to include a first upper conductive pattern and a second upper conductive pattern with connectivity to the first lower conductive pattern and the second lower conductive pattern as taught by Im in order to provide greater connectivity across the device, increase device reliability, and to allow quicker computing rates.
Regarding claim 16. Takeya as modified discloses wherein each of the plurality of fourth lower conductive patterns is configured to have only a first driving voltage applied, and each of plurality of the plurality of first lower conductive patterns, the plurality of second lower conductive patterns, and the plurality of third lower conductive patterns is configured to have a gate voltage or a second driving voltage applied ([0072], figure 1, the plurality of fourth lower conductive patterns #122 is conductive, therefore they are ‘configured to’ have a voltage applied to it, thus reading on a first driving voltage. The plurality of first lower conductive pattern #122a, second lower conductive pattern #122b, and the third lower conductive pattern #122c are conductive, therefore they are ‘configured to’ have a voltage applied to it, thus reading on a gate voltage).
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Regarding claim 17. Takeya as modified discloses wherein in each of the plurality of pixels, a plurality of first pads, a plurality of second pads, and a plurality of third pads are formed,
each of the plurality of first lower conductive patterns is electrically connected to the first pad through a first contact hole,
each of the plurality of second lower conductive patterns is electrically connected to the second pad through a second contact hole,
each of the plurality of third lower conductive patterns is electrically connected to the third pad through a third contact hole, and
each of the plurality of fourth lower conductive patterns is electrically connected to the vertical light emitting diode ([0080], figure 1 annotated above, in each plurality of pixels #112a-112c, a plurality of a first pad #134a, second pad #134b, and a third pad #134c is formed (please note the plurality of pads needed for the grid seen in figure 2). The first lower conductive pattern #122a is connected to the first pad #134a through a first contact hole which #152 fills in and allows conductivity through. please note the contact hole is made to the element #150 in which #152 fills in for. The second lower conductive pattern #122b is connected to the second pad #134b through a second contact hole which #152 fills in and allows conductivity through. The third lower conductive pattern #122c is connected to the third pad #134c through a third contact hole which #152 fills in and allows conductivity through. The fourth lower conductive pattern #122d is directly connected to the vertical light emitting diode #112a (please note the plurality of lower conductive patterns needed for the grid seen in figure 2)).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Takeya et al. (US-20220384406-A1 referred as Takeya) and Kim (US-20080278070-A1) and Im et al. (US-20220375990-A1 referred as Im) as applied to claim 15, in further view of Ahn et al. (US-20200211437-A1 referred as Ahn).
Regarding claim 18. Takeya as modified discloses wherein each of the plurality of upper connection lines includes a first upper connection line and a second upper connection line disposed on the second layer ([0080], figure 1 annotated above, the plurality of upper connection lines #152 includes a first upper connection line #152a and a second upper connection line #152b disposed on a second layer), the first upper connection line connects a first upper conductive patterns, the second upper connection line connects a second upper conductive patterns ([0063], figure 1 annotated above, the first upper connection line #152a connects to the first upper conductive patterns #122a, and the second upper connection line #152b is connected to the second upper conductive patterns #122b).
Takeya as modified lacks wherein each of the plurality of upper connection lines includes a third upper connection line and a fourth upper connection line disposed on the first layer, and the third upper connection line connects a third lower conductive patterns, and the fourth upper connection line connects a fourth lower conductive patterns.
Ahn discloses wherein each of the plurality of upper connection lines includes a third upper connection line and a fourth upper connection line disposed on the first layer ([0112], figure 4, the plurality of upper connection lines includes a third upper connection line #143 and a fourth upper connection line #144 disposed on the first layer #115), and the third upper connection line connects a third lower conductive patterns, and the fourth upper connection line connects a fourth lower conductive patterns ([0112], figure 4, the third upper connection line #143 is connected to the third lower conductive pattern #153 and the fourth upper connection line #144 is connected to the fourth lower conductive pattern #154).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Takeya to include a third upper connection line and a fourth upper connection line with connectivity to the third lower conductive patterns and the fourth lower conductive patterns as taught by Ahn in order to provide greater versatility for its use, increase device reliability, and to allow quicker manufacturing rate.
Regarding claim 19. Takeya as modified discloses wherein the first upper connection line, the second upper connection line, the third upper connection line, and the fourth upper connection line extend only in a first direction (figure 1 annotated above, the first upper connection line #152a, a second upper connection line #152b, a third upper connection line #152c, and the fourth upper connection line #152d extend only in a first direction (vertical)).
Regarding claim 20. Takeya as modified discloses wherein the plurality of lower connection lines extends only in a second direction different from the first direction (figure 1, the plurality of lower connection lines #116 extend only in a second direction (horizontal)), and each of the plurality of lower connection lines is configured to have a data voltage applied ([0072], figure 1, the plurality of lower connection lines #116 is conductive, therefore they are ‘configured to’ have a voltage applied to it, thus reading on a data voltage).
Response to Amendment
Applicant's arguments filed 03/16/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art by new prior art, Kim (US-20080278070). All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
For claim 1 .... "Applicant's amendments and arguments were persuasive. Upon further search and consideration a new rejection using a different interpretation of Takeya et al. in combination with newly cited reference to Kim has been presented with regard to claim 1."
For page 12 of the arguments, Applicant states that it would not have been easy to combine Tokeya et al and Cho et al. due to the structurally different inventions. Although that it is agreed that both arts are different inventions, the claim language reads for the proximity of the upper line patterns and the type of elasticity the material contains which is what is combined, not the full invention, therefore, the combination is proper in relation to display devices and the design described in Cho would aid to increase device versatility, reduce device failure, and to increase the circuits lifetime (as stated in the rejection above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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